Inventor

Mark E. Jost

Inventor

Boise, ID, US

Overview

1992–2011

Patent span

Electricity

Primary field (CPC H)

Patents· 52 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1025%

H10BElectronic memory devices18%

H10DInorganic electric semiconductor devices18%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests15%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices5%

C23CCoating metallic material1%

H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light1%

B82YSpecific uses or applications of nanostructures1%

G02BOptical elements, systems or apparatus1%

PatentTitleYear

7,955,976'Methods of forming semiconductor structures'2011 7,659,630'Interconnect structures with interlayer dielectric'2010 7,326,647'Dry etching process to form a conductive layer within an opening without use of a mask during the formation of a semiconductor device'2008 7,279,414'Method of forming interconnect structure with interlayer dielectric'2007 6,982,228'Methods of etching a contact opening over a node location on a semiconductor substrate'2006 6,828,252'Method of etching a contact opening'2004 6,790,762'Method of making an electrical device including an interconnect structure'2004 6,787,472'Utilization of disappearing silicon hard mask for fabrication of semiconductor structures'2004 6,689,693'Methods for utilization of disappearing silicon hard mask for fabrication of semiconductor structures'2004 6,653,241'Methods of forming protective segments of material, and etch stops'2003 6,620,734'Methods of forming protective segments of material, and etch stops'2003 6,605,516'Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns'2003 6,596,641'Chemical vapor deposition methods'2003 6,534,408'Utilization of disappearing silicon hard mask for fabrication of semiconductor structures'2003 6,461,963'Utilization of disappearing silicon hard mask for fabrication of semiconductor structures'2002 6,418,008'Enhanced capacitor shape'2002 6,391,709'Enhanced capacitor shape'2002 6,369,432'Enhanced capacitor shape'2002 6,355,566'Method of removing surface defects or other recesses during the formation of a semiconductor device'2002 6,228,772'Method of removing surface defects or other recesses during the formation of a semiconductor device'2001 6,207,529'Semiconductor wafer,wafer alignment patterns and method of forming wafer alignment patterns'2001 6,153,527'Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material'2000 6,150,257'Plasma treatment of an interconnect surface during formation of an interlayer dielectric'2000 6,137,186'Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns'2000 6,127,239'Semiconductor processing methods, and methods of forming capacitors'2000 6,110,774'Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells'2000 6,046,094'Method of forming wafer alignment patterns'2000 6,037,261'Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material'2000 6,025,271'Method of removing surface defects or other recesses during the formation of a semiconductor device'2000 6,010,941'Method of forming a capacitor'2000 5,994,237'Semiconductor processing methods of forming a contact opening to a semiconductor substrate'1999 5,966,611'Semiconductor processing for forming capacitors by etching polysilicon and coating layer formed over the polysilicon'1999 5,962,885'Method of forming a capacitor and a capacitor construction'1999 5,925,937'Semiconductor wafer, wafer alignment patterns'1999 5,900,660'Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory calls'1999 5,888,877'Method of forming recessed container cells'1999 5,869,403'Semiconductor processing methods of forming a contact opening to a semiconductor substrate'1999 5,821,140'Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells'1998 5,798,292'Method of forming wafer alignment patterns'1998 5,789,304'Method of forming a capacitor'1998 5,739,068'Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material'1998 5,705,838'Array of bit line over capacitor array of memory cells'1998 5,702,990'Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells'1997 5,700,732'Semiconductor wafer, wafer alignment patterns and method of forming wafer alignment patterns'1997 5,686,747'Integrated circuits comprising interconnecting plugs'1997 5,605,857'Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells'1997 5,604,147'Method of forming a cylindrical container stacked capacitor'1997 5,563,089'Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells'1996 5,311,539'Roughened sidewall ridge for high power fundamental mode semiconductor ridge waveguide laser operation'1994 5,307,357'Protection means for ridge waveguide laser structures using thick organic films'1994 5,258,318'Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon'1993 5,128,271'High performance vertical bipolar transistor structure via self-aligning processing techniques'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–1994Patents assigned to IBM (4)· patent assignee history

1992Based in Adliswill, CH· patent location history

1993–1994Based in Fishkill, NY, US· patent location history

1996–2011Patents assigned to MICRON TECHNOLOGY INC (47)· patent assignee history

1996–2011Based in Boise, ID, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	47	1996–2011
IBM	4	1992–1994

Locations

Location	Patents	Span
Boise, ID, US	48	1996–2011
Fishkill, New York, US	3	1993–1994
Adliswill, CH	1	1992