Inventor
Peter G. Tolchinsky
Inventor
Beaverton, OR, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1032%
H10DInorganic electric semiconductor devices29%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H01LSemiconductor devices10%
B82YSpecific uses or applications of nanostructures4%
B23KSoldering or unsoldering3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
H04BTransmission1%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%
PatentTitleYear
10,879,134Techniques for monolithic co-integration of silicon and III-N semiconductor transistors202010,692,839GaN devices on engineered silicon substrates202010,600,787Silicon PMOS with gallium nitride NMOS for voltage regulation20209,711,591'Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed thereby'20179,691,843'Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition'20179,691,632'Epitaxial wafer and a method of manufacturing thereof'20179,559,160'Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition'20178,617,945'Stacking fault and twin blocking barrier for integrating III-V on Si'20138,217,383'High hole mobility p-channel Ge transistor structure on Si substrate'20128,143,646'Stacking fault and twin blocking barrier for integrating III-V on Si'20127,863,710'Dislocation removal from a group III-V film grown on a semiconductor substrate'20117,851,781'Buffer layers for device isolation of devices grown on silicon'20107,791,063'High hole mobility p-channel Ge transistor structure on Si substrate'20107,687,799'Methods of forming buffer layer architecture on silicon and structures formed thereby'20107,670,928'Ultra-thin oxide bonding for S1 to S1 dual orientation bonding'20107,573,059'Dislocation-free InSb quantum well structure on Si using novel buffer architecture'20097,569,857'Dual crystal orientation circuit devices on the same substrate'20097,531,429'Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices'20097,494,911'Buffer layers for device isolation of devices grown on silicon'20097,491,988'Transistors with increased mobility in the channel zone and method of fabrication'20097,473,614'Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer'20097,378,331'Methods of vertically stacking wafers using porous silicon'20087,161,224'Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process'20077,091,108'Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices'20067,042,009'High mobility tri-gate devices and methods of fabrication'20066,924,543'Method for making a semiconductor device having increased carrier mobility'20056,911,380'Method of forming silicon on insulator wafers'20056,908,027'Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2020Patents assigned to INTEL CORP (28)· patent assignee history
2005–2020Based in Beaverton, OR, US· patent location history
2006Based in Portland, OR, US· patent location history
2012–2017Patents assigned to TOLCHINSKY PETER G (5)· patent assignee history
2012–2013Patents assigned to HUDAIT MANTU K (3)· patent assignee history
2012–2013Patents assigned to CHOW LOREN A (2)· patent assignee history
2012–2013Patents assigned to FASTENAU JOEL M (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 28 | 2005–2020 |
| TOLCHINSKY PETER Gself | 5 | 2012–2017 |
| HUDAIT MANTU K | 3 | 2012–2013 |
| CHOW LOREN A | 2 | 2012–2013 |
| FASTENAU JOEL M | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 27 | 2005–2020 |
| Portland, OR, US | 1 | 2006 |