Inventor
Jen-Tai Hsu
Inventor
San Jose, CA, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique28%
G11CStatic stores22%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems17%
G05FSystems for regulating electric or magnetic variables8%
H04LTransmission of digital information, e.g. telegraphic communication8%
G01RMeasuring electric variables3%
G06FElectric digital data processing3%
H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner3%
H03HImpedance networks, e.g. resonant circuits3%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%
PatentTitleYear
10,770,153Charge pump drive circuit with two switch signals202010,748,618Local X-decoder and related memory system with a voltage clamping transistor202010,684,316Voltage detection circuit for charge pump202010,650,866Charge pump drive circuit202010,606,299Circuit for regulating leakage current in charge pump202010,515,705Removing pump noise in a sensing circuit201910,498,215Voltage regulator with flexible output voltage201910,482,968Local x-decoder and related memory system201910,482,967Layout structure of local x-decoder201910,340,793Digital control of charge pump20198,928,380'Current-mode D latch with reset function and associated circuit'20158,547,149'Clock and data recovery system'20138,488,731'Slicing level and sampling phase adaptation circuitry for data recovery systems'20138,400,226'Oscillation circuit and associated method'20137,356,796'Method and apparatus to boost high-speed I/O signal performance using semi-interleaved transmitter/receiver pairs at silicon die bump and package layout interfaces'20087,245,682'Determining an optimal sampling clock'20076,556,022'Method and apparatus for local parameter variation compensation'20036,507,218'Method and apparatus for reducing back-to-back voltage glitch on high speed data bus'20036,445,316'Universal impedance control for wide range loaded signals'20026,380,758'Impedance control for wide range loaded signals using distributed methodology'20026,313,661'High voltage tolerant I/O buffer'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2008Patents assigned to INTEL CORP (7)· patent assignee history
2001–2008Based in El Dorado Hills, CA, US· patent location history
2013–2015Patents assigned to GLOBAL UNICHIP CORP (4)· patent assignee history
2013Patents assigned to HSU JEN-TAI (3)· patent assignee history
2013Patents assigned to AN FU-TAI (2)· patent assignee history
2013–2015Based in Miao-Li County, TW· patent location history
2013Based in Miaoli, TW· patent location history
2019–2020Patents assigned to WUHAN XINXIN SEMICONDUCTOR MFG (10)· patent assignee history
2019–2020Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| WUHAN XINXIN SEMICONDUCTOR MFG | 10 | 2019–2020 |
| INTEL CORP | 7 | 2001–2008 |
| GLOBAL UNICHIP CORP | 4 | 2013–2015 |
| HSU JEN-TAIself | 3 | 2013 |
| AN FU-TAI | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 10 | 2019–2020 |
| El Dorado Hills, California, US | 7 | 2001–2008 |
| Miao-Li County, TW | 2 | 2013–2015 |
| Miaoli, TW | 2 | 2013 |