Inventor
Thomas E. Obremski
Inventor
South Burlington, VT, US
Overview
Patents· 6 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores75%
G01RMeasuring electric variables13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
PatentTitleYear
7,237,165'Method for testing embedded DRAM arrays'20077,103,814'Testing logic and embedded memory in parallel'20067,073,100'Method for testing embedded DRAM arrays'20066,452,848'Programmable built-in self test (BIST) data generator for semiconductor memory devices'20026,388,930'Method and apparatus for ram built-in self test (BIST) address generation using bit-wise masking of counters'20025,724,295'Partitioned dynamic memory allowing substitution of a redundant circuit in any partition and using partial address disablement and disablement override'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2007Patents assigned to IBM (6)· patent assignee history
1998–2007Based in South Burlington, VT, US· patent location history
2006Based in Burlington, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 6 | 1998–2007 |
Locations
| Location | Patents | Span |
|---|---|---|
| South Burlington, VT, US | 5 | 1998–2007 |
| Burlington, VT, US | 1 | 2006 |