Inventor
Badredin Fatemizadeh
Inventor
Sunnyvale, CA, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices35%
H01LSemiconductor devices22%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems8%
H10BElectronic memory devices4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications4%
G11CStatic stores2%
H03KPulse technique2%
PatentTitleYear
10,964,694Multi-transistor device including first and second LDMOS transistors having respective drift regions separated in a thickness direction by a shared RESURF layer202110,833,164LDMOS transistors and associated systems and methods202010,622,452Transistors with dual gate conductors, and associated methods202010,573,744Self-aligned, dual-gate LDMOS transistors and associated methods202010,284,072Voltage regulators with multiple transistors201910,269,916LDMOS transistors and associated systems and methods201910,229,993LDMOS transistors including resurf layers and stepped-gates, and associated systems and methods201910,199,475LDMOS transistors and associated systems and methods201910,147,801Transistor with buried P+ and source contact20189,722,483'Voltage regulators with multiple transistors'20179,159,804'Vertical gate LDMOS device'20158,969,158'Vertical gate LDMOS device'20158,866,217'Vertical gate LDMOS device'20148,709,899'Vertical gate LDMOS device'20148,647,950'Vertical gate LDMOS device'20147,235,827'Vertical power JFET with low on-resistance for high voltage applications'20077,049,677'Low cost dielectric isolation method for integration of vertical power MOSFET and lateral driver devices'20066,872,602'Carrier coupler for thyristor-based semiconductor device'20056,756,612'Carrier coupler for thyristor-based semiconductor device'20046,242,972'Clamp circuit using PMOS-transistors with a weak temperature dependency'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2019Based in Sunnyvale, CA, US· patent location history
2004–2007Based in San Jose, CA, US· patent location history
2014–2019Patents assigned to Volterra Semiconductor LLC (5)· patent assignee history
2014–2018Patents assigned to FATEMIZADEH BADREDIN (4)· patent assignee history
2014–2018Patents assigned to LU YANG (4)· patent assignee history
2014–2018Patents assigned to PAUL AMIT (4)· patent assignee history
2019–2021Patents assigned to MAXIM INTEGRATED PRODUCTS (7)· patent assignee history
2019–2021Based in Palo Alto, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MAXIM INTEGRATED PRODUCTS | 7 | 2019–2021 |
| Volterra Semiconductor LLC | 5 | 2014–2019 |
| FATEMIZADEH BADREDINself | 4 | 2014–2018 |
| LU YANG | 4 | 2014–2018 |
| PAUL AMIT | 4 | 2014–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sunnyvale, California, US | 9 | 2001–2019 |
| Palo Alto, California, US | 7 | 2019–2021 |
| San Jose, California, US | 4 | 2004–2007 |