Inventor
Scott Balster
Inventor
Munich, DE
Overview
Patents· 40 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices53%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H01LSemiconductor devices9%
C23CCoating metallic material1%
H01CResistors1%
H10BElectronic memory devices1%
PatentTitleYear
10,937,905Transistor having double isolation with one floating isolation202110,319,809Structures to avoid floating resurf layer in high voltage lateral devices20199,985,028Diluted drift layer with variable stripe widths for power transistors20189,876,071Structures to avoid floating RESURF layer in high voltage lateral devices20189,653,577'Diluted drift layer with variable stripe widths for power transistors'20179,431,480'Diluted drift layer with variable stripe widths for power transistors'20168,847,359'High voltage bipolar transistor and method of fabrication'20148,703,568'Advanced CMOS using super steep retrograde wells'20148,450,179'Semiconductor device having a first bipolar device and a second bipolar device and method for fabrication'20138,294,218'Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection'20128,247,300'Control of dopant diffusion from buried layers in bipolar integrated circuits'20128,129,246'Advanced CMOS using super steep retrograde wells'20128,012,842'Method for fabricating isolated integrated semiconductor structures'20117,883,977'Advanced CMOS using super steep retrograde wells'20117,772,057'Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection'20107,736,986'Integrated stacked capacitor and method of fabricating same'20107,670,890'Silicide block isolated junction field effect transistor source, drain and gate'20107,655,523'Advanced CMOS using super steep retrograde wells'20107,501,324'Advanced CMOS using super steep retrograde wells'20097,498,639'Integrated BiCMOS semiconductor circuit'20097,422,972'On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits'20087,312,119'Stacked capacitor and method of fabricating same'20077,227,241'Integrated stacked capacitor and method of fabricating same'20077,217,322'Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer'20077,199,430'Advanced CMOS using super steep retrograde wells'20077,192,838'Method of producing complementary SiGe bipolar transistors'20077,164,186'Structure of semiconductor device with sinker contact region'20077,144,789'Method of fabricating complementary bipolar transistors with SiGe base regions'20067,130,182'Stacked capacitor and method for fabricating same'20067,118,981'Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor'20067,064,399'Advanced CMOS using super steep retrograde wells'20066,958,523'On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits'20056,894,366'Bipolar junction transistor with a counterdoped collector region'20056,838,348'Integrated process for high voltage and high performance silicon-on-insulator bipolar devices'20056,806,159'Method for manufacturing a semiconductor device with sinker contact region'20046,774,455'Semiconductor device with a collector contact in a depressed well-region'20046,770,952'Integrated process for high voltage and high performance silicon-on-insulator bipolar devices'20046,646,323'Zero mask high density metal/insulator/metal capacitor'20036,407,425'Programmable neuron MOSFET on SOI'20026,391,707'Method of manufacturing a zero mask high density metal/insulator/metal capacitor'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2021Patents assigned to TEXAS INSTRUMENTS INC (39)· patent assignee history
2002–2012Based in Munich, DE· patent location history
2005Based in Richardson, TX, US· patent location history
2007–2021Based in Dallas, TX, US· patent location history
2012–2014Patents assigned to BABCOCK JEFFREY A (3)· patent assignee history
2012–2014Patents assigned to BALSTER SCOTT (3)· patent assignee history
2012–2014Patents assigned to EL-KAREH BADIH (3)· patent assignee history
2012–2014Patents assigned to HOWARD GREGORY E (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 39 | 2002–2021 |
| BABCOCK JEFFREY A | 3 | 2012–2014 |
| BALSTER SCOTTself | 3 | 2012–2014 |
| EL-KAREH BADIH | 3 | 2012–2014 |
| HOWARD GREGORY E | 3 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Munich, DE | 21 | 2002–2012 |
| Dallas, Texas, US | 18 | 2007–2021 |
| Richardson, Texas, US | 1 | 2005 |