Inventor
Kenneth L. Ward
Inventor
Austin, TX, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing83%
G01RMeasuring electric variables8%
B62DMotor vehicles4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
PatentTitleYear
10,877,763Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor202010,831,492Most favored branch issue202010,831,489Mechanism for completing atomic instructions in a microprocessor202010,761,856Instruction completion table containing entries that share instruction tags202010,725,786Completion mechanism for a microprocessor instruction completion table202010,713,057Mechanism to stop completions using stop codes in an instruction completion table202010,552,165Efficiently managing speculative finish tracking and error handling for load instructions202010,423,423Efficiently managing speculative finish tracking and error handling for load instructions201910,169,046Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction201910,108,423History buffer with single snoop tag for multiple-field registers20189,996,353Universal history buffer to support multiple register types20189,971,687Operation of a multi-slice processor with history buffers storing transaction memory state information20189,971,604History buffer for multiple-field registers20189,798,549'Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction'20177,870,406'Method and apparatus for frequency independent processor utilization recording register in a simultaneously multi-threaded processor'20117,865,758'Fault tolerant time synchronization mechanism in a scaleable multi-processor computer'20117,761,726'Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer'20107,603,497'Method and apparatus to launch write queue read data in a microprocessor recovery unit'20097,526,583'Method and apparatus to launch write queue read data in a microprocessor recovery unit'20097,487,377'Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer'20097,409,589'Method and apparatus for reducing number of cycles required to checkpoint instructions in a multi-threaded processor'20085,805,836'Method and apparatus for equalizing grants of a data bus to primary and secondary devices'19985,752,734'Rail components for pick-up or flat-bed trucks to support side or back pieces'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2020Patents assigned to IBM (22)· patent assignee history
1998–2020Based in Austin, TX, US· patent location history
1998Based in Machesney Park, IL, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 22 | 1998–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 22 | 1998–2020 |
| Machesney Park, Illinois, US | 1 | 1998 |