Inventor
Fu-Lung Hsueh
Inventor
Kaohsiung, TW
Overview
Patents· 128 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices11%
H01LSemiconductor devices11%
H03KPulse technique9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
G11CStatic stores5%
G06FElectric digital data processing5%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses5%
H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner4%
H03MCoding4%
H01FMagnets3%
PatentTitleYear
11,128,285Input/output circuit and method202110,855,280Input/output circuit and method202010,854,708Capacitor having multiple graphene structures202010,785,865Interconnect structure and method of manufacturing the same202010,756,672Varainductor having ground and floating planes202010,686,434Input/output circuit202010,672,969Thermocouple device202010,673,437Level shifting circuit and method202010,530,030Semiconductor device having first and second transmission lines with a high-K dielectric material disposed between the first and second transmission lines202010,510,827Capacitor having multiple graphene structures201910,289,777Integrated circuit designs based on temperature distribution determination201910,187,046Input/output circuit201910,177,764Input/output circuit201910,165,208Method for reducing blooming in image sensor during idle period201810,050,104Capacitor having a graphene structure, semiconductor device including the capacitor and method of forming the same201810,044,547Digital code recovery with preamble201810,031,161Method and apparatus for RFID tag testing201810,027,304Dual-band band-pass filters and method of use20189,978,796Methods for forming dual-side illumination image sensor chips20189,954,488Varainductor, voltage controlled oscillator including the varainductor, and phase locked loop including the varainductor20189,899,982'On-chip electromagnetic bandgap (EBG) structure for noise suppression'20189,887,189'Integrated circuits with resistors'20189,812,251'Varainductor and operation method thereof based on mutual capacitance'20179,807,867'Interconnect structure and method of manufacturing the same'20179,800,154'Voltage supply unit and method for operating the same'20179,786,976'Transmission line design and method, where high-k dielectric surrounds the transmission line for increased isolation'20179,761,553'Inductor with conductive trace'20179,712,145'Delay line circuit with variable delay line unit'20179,698,146'Multi-gate and complementary varactors in FinFET process'20179,628,102'Integrated circuits, liquid crystal display (LCD) drivers, and systems'20179,607,121'Cascode CMOS structure'20179,559,686'Input/output circuit'20179,548,267'Three dimensional circuit including shielded inductor and method of forming same'20179,531,350'Level shifters for IO interfaces'20169,529,955'Integrated circuit layout'20169,524,934'Integrated circuits with electrical fuses and methods of forming the same'20169,478,344'Phase locked loop including a varainductor'20169,450,573'Input/output circuit'20169,432,030'Circuit and operating method of PLL'20169,426,393'Noise simulation flow for low noise CMOS image sensor design'20169,419,617'Circuit for reducing negative bias temperature instability'20169,412,721'Contactless communications using ferromagnetic material'20169,397,729'Through chip coupling for signal transport'20169,391,626'Capacitive load PLL with calibration loop'20169,360,876'Voltage supply circuit having an absorption unit and method for operating the same'20169,350,324'MCML retention flip-flop/latch for low power applications'20169,304,164'Method and apparatus for RFID tag testing'20169,299,699'Multi-gate and complementary varactors in FinFET process'20169,275,598'DAC architecture for LCD source driver'20169,270,908'Image sensor configured to reduce blooming during idle period'20169,255,963'Built-in self-test circuit for voltage controlled oscillator'20169,214,933'Input/output circuit'20159,203,387'Delay line circuit with variable delay line unit'20159,202,963'Dual-side illumination image sensor chips and methods for forming the same'20159,171,839'Integrated circuits with resistors'20159,165,968'3D-stacked backside illuminated image sensor and method of making the same'20159,129,940'RF calibration through-chip inductive coupling'20159,098,757'Method and apparatus of RFID tag contactless testing'20159,048,127'Three dimensional circuit including shielded inductor and method of forming same'20158,981,979'Integrated circuits, liquid crystal display (LCD) drivers, and systems'20158,957,482'Electrical fuse and related applications'20158,890,626'Divider-less phase locked loop (PLL)'20148,885,787'Clock and data recovery using LC voltage controlled oscillator and delay locked loop'20148,857,260'Motion detection using capacitor having different work function materials'20148,847,321'Cascode CMOS structure'20148,847,652'Reconfigurable and auto-reconfigurable resonant clock'20148,835,246'Integrated circuits with resistors and methods of forming the same'20148,816,732'Capactive load PLL with calibration loop'20148,791,720'Circuit for reducing negative bias temperature instability'20148,762,897'Semiconductor device design system and method of using the same'20148,760,255'Contactless communications using ferromagnetic material'20148,729,968'Built-in self-test circuit for voltage controlled oscillators'20148,709,684'Automatic misalignment balancing scheme for multi-patterning technology'20148,703,571'Methods of fabricating bipolar junction transistors having a fin'20148,698,566'Phase locked loop calibration'20148,661,389'Systems and methods of designing integrated circuits'20148,648,779'LCD driver'20148,627,253'Method for substrate noise analysis'20148,619,488'Multi-level electrical fuse using one programming device'20138,588,358'Clock and data recovery using LC voltage controlled oscillator and delay locked loop'20138,570,068'Circuit for reducing negative bias temperature instability'20138,549,922'Motion detection using capacitor having different work function materials'20138,539,388'Method and apparatus for low power semiconductor chip layout and low power semiconductor chip'20138,493,124'Low minimum power supply voltage level shifter'20138,476,972'Method and apparatus for amplifying a time difference'20138,451,033'Millimeter-wave wideband frequency doubler'20138,450,672'CMOS image sensors formed of logic bipolar transistors'20138,436,671'Level shifters having diode-connected devices for input-output interfaces'20138,432,204'Current-controlled oscillator (CCO) based PLL'20138,427,240'Low-noise amplifier with gain enhancement'20138,418,098'Advisory system for verifying sensitive circuits in chip-design'20138,334,571'Junction varactor for ESD protection of RF circuits'20128,324,970'Circuit and method for radio frequency amplifier'20128,324,658'ESD protection circuit for RFID tag'20128,305,790'Electrical anti-fuse and related applications'20128,295,018'Transmission-line-based ESD protection'20128,279,008'CMOS millimeter-wave variable-gain low-noise amplifier'20128,264,288'Quadrature voltage controlled oscillator including transmission line'20128,258,879'Capacitor coupled quadrature voltage controlled oscillator'20128,258,602'Bipolar junction transistors having a fin'20128,217,729'Integrated circuits including an LC tank circuit and operating methods thereof'20128,207,775'VOL up-shifting level shifters'20128,193,963'Method and system for time to digital conversion with calibration and correction loops'20128,183,910'Circuit and method for a digital process monitor'20128,143,644'Bipolar device compatible with CMOS process technology'20128,030,181'Electrical fuse circuit for security applications'20117,968,971'Thin-body bipolar device'20117,919,832'Stack resistor structure for integrated circuits'20117,843,747'System and method for better testability of OTP memory'20107,821,041'Electrical fuse circuit for security applications'20107,782,656'SRAM with improved read/write stability'20107,746,142'Circuit and method for clock skew compensation in voltage scaling'20107,663,445'Voltage-control oscillator circuits with combined MOS and bipolar device'20107,633,415'System and method for calibrating digital-to-analog convertors'20097,612,638'Waveguides in integrated circuits'20097,577,020'System and method for reading multiple magnetic tunnel junctions with a single select transistor'20097,564,295'Automatic bias circuit for sense amplifier'20097,501,966'Digital-to-analog converter cell'20097,394,637'Sense amplifier with leakage compensation for electrical fuses'20087,369,076'High precision DAC with thermometer coding'20087,310,281'Semiconductor memories with refreshing cycles'20077,075,472'Averaging analog-to-digital converter with shared capacitor network'20066,608,580'Differential analog-to-digital converter'20036,229,506'Active matrix light emitting diode pixel structure and concomitant method'20016,104,041'Switching circuitry layout for an active matrix electroluminescent display pixel with each pixel provided with the transistors'20005,291,198'Averaging flash analog-to-digital converter'19945,014,055'Analog-to-digital converter and method of use utilizing charge redistribution'19914,725,875'Memory cell with diodes providing radiation hardness'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2018Based in Cranbury, NJ, US· patent location history
2006–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (73)· patent assignee history
2008–2018Based in Hsinchu, TW· patent location history
2009–2016Patents assigned to HSUEH FU-LUNG (49)· patent assignee history
2010–2015Based in Cranberry, NJ, US· patent location history
2012–2016Patents assigned to JOU CHEWN-PU (18)· patent assignee history
2012–2016Patents assigned to CHERN CHAN-HONG (14)· patent assignee history
2013–2021Based in Kaohsiung, TW· patent location history
2015–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (48)· patent assignee history
2015–2017Based in Kaohisung, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 73 | 2006–2016 |
| HSUEH FU-LUNGself | 49 | 2009–2016 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 48 | 2015–2021 |
| JOU CHEWN-PU | 18 | 2012–2016 |
| CHERN CHAN-HONG | 14 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kaohsiung, TW | 56 | 2013–2021 |
| Cranbury, New Jersey, US | 48 | 2000–2018 |
| Hsinchu, TW | 14 | 2008–2018 |
| Cranberry, New Jersey, US | 3 | 2010–2015 |
| Kaohisung, TW | 2 | 2015–2017 |