LexDanaLexDanabeta
Inventor

Sagy Levy

Inventor
Zichron Yaakov, IL

Overview

64→
Patents
2001–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 64 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices31%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H01LSemiconductor devices17%
H10BElectronic memory devices10%
G11CStatic stores8%
B82YSpecific uses or applications of nanostructures8%
C23CCoating metallic material3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
G05FSystems for regulating electric or magnetic variables1%
PatentTitleYear
10,699,901SONOS ONO stack scaling202010,615,289Nonvolatile charge trap memory device having a high dielectric constant blocking region202010,593,812Radical oxidation process for fabricating a nonvolatile charge trap memory device202010,446,656Memory transistor with multiple charge storing layers and a high work function gate electrode201910,411,103Memory transistor with multiple charge storing layers and a high work function gate electrode201910,374,067Oxide-nitride-oxide stack having multiple oxynitride layers201910,312,336Memory transistor with multiple charge storing layers and a high work function gate electrode201910,304,968Radical oxidation process for fabricating a nonvolatile charge trap memory device201910,269,985Radical oxidation process for fabricating a nonvolatile charge trap memory device201910,263,087Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region201910,217,826Apparatus of a metal-oxide-semiconductor (MOS) transistor including a multi-split gate201910,090,416Radical oxidation process for fabricating a nonvolatile charge trap memory device201810,079,314Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region20189,997,641SONOS ONO stack scaling20189,929,240'Memory transistor with multiple charge storing layers and a high work function gate electrode'20189,899,486'Memory transistor with multiple charge storing layers and a high work function gate electrode'20189,837,411Semiconductor die with a metal via20179,812,566'LDMOS device having a low angle sloped oxide'20179,806,174'Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure'20179,741,803'Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region'20179,716,153'Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region'20179,553,175'SONOS type stacks for nonvolatile charge trap memory devices and methods to form the same'20179,502,543'Method of manufacturing for memory transistor with multiple charge storing layers and a high work function gate electrode'20169,484,454'Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure'20169,449,831'Oxide-nitride-oxide stack having multiple oxynitride layers'20169,431,549'Nonvolatile charge trap memory device having a high dielectric constant blocking region'20169,355,849'Oxide-nitride-oxide stack having multiple oxynitride layers'20169,349,877'Nitridation oxidation of tunneling layer for improved SONOS speed and retention'20169,349,824'Oxide-nitride-oxide stack having multiple oxynitride layers'20169,306,025'Memory transistor with multiple charge storing layers and a high work function gate electrode'20169,299,568'SONOS ONO stack scaling'20169,105,740'SONOS type stacks for nonvolatile changetrap memory devices and methods to form the same'20159,105,712'Double RESURF LDMOS with separately patterned P+ and N+ buried layers formed by shared mask'20159,093,318'Memory transistor with multiple charge storing layers and a high work function gate electrode'20158,993,453'Method of fabricating a nonvolatile charge trap memory device'20158,940,645'Radical oxidation process for fabricating a nonvolatile charge trap memory device'20158,871,595'Integration of non-volatile charge trap memory devices and logic CMOS devices'20148,859,374'Memory transistor with multiple charge storing layers and a high work function gate electrode'20148,860,122'Nonvolatile charge trap memory device having a high dielectric constant blocking region'20148,691,648'Methods for fabricating semiconductor memory with process induced strain'20148,679,927'Integration of non-volatile charge trap memory devices and logic CMOS devices'20148,680,601'Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region'20148,643,124'Oxide-nitride-oxide stack having multiple oxynitride layers'20148,637,921'Nitridation oxidation of tunneling layer for improved SONOS speed and retention'20148,633,537'Memory transistor with multiple charge storing layers and a high work function gate electrode'20148,614,124'SONOS ONO stack scaling'20138,592,891'Methods for fabricating semiconductor memory with process induced strain'20138,318,608'Method of fabricating a nonvolatile charge trap memory device'20128,163,660'SONOS type stacks for nonvolatile change trap memory devices and methods to form the same'20128,093,128'Integration of non-volatile charge trap memory devices and logic CMOS devices'20128,088,683'Sequential deposition and anneal of a dielectic layer in a charge trapping memory device'20128,067,284'Oxynitride bilayer formed using a precursor inducing a high charge trap density in a top layer of the bilayer'20118,063,434'Memory transistor with multiple charge storing layers and a high work function gate electrode'20117,898,852'Trapped-charge non-volatile memory with uniform multilevel programming'20117,880,219'Nonvolatile charge trap memory device having <100> crystal plane channel orientation'20117,799,670'Plasma oxidation of a memory layer to form a blocking layer in non-volatile charge trap memory devices'20107,670,963'Single-wafer process for fabricating a nonvolatile charge trap memory device'20107,446,063'Silicon nitride films'20087,384,833'Stress liner for integrated circuits'20086,884,719'Method for depositing a coating having a relatively high dielectric constant onto a substrate'20056,638,876'Method of forming dielectric films'20036,451,713'UV pretreatment process for ultra-thin oxynitride formation'20026,204,120'Semiconductor wafer pretreatment utilizing ultraviolet activated chlorine'20016,191,011'Selective hemispherical grain silicon deposition'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2014Based in Sunnyvale, CA, US· patent location history
2008–2019Patents assigned to CYPRESS SEMICONDUCTOR CORP (43)· patent assignee history
2010–2014Based in Yaakov, IL· patent location history
2010Based in Yaskov, IL· patent location history
2011–2017Patents assigned to LEVY SAGY (22)· patent assignee history
2011–2017Patents assigned to RAMKUMAR KRISHNASWAMY (19)· patent assignee history
2011–2016Patents assigned to POLISHCHUK IGOR (8)· patent assignee history
2011–2020Based in Zichron Yaakov, IL· patent location history
2015–2019Patents assigned to TOWER SEMICONDUCTOR LTD (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
CYPRESS SEMICONDUCTOR CORP432008–2019
LEVY SAGYself222011–2017
RAMKUMAR KRISHNASWAMY192011–2017
POLISHCHUK IGOR82011–2016
TOWER SEMICONDUCTOR LTD62015–2019
Locations
LocationPatentsSpan
Zichron Yaakov, IL482011–2020
Sunnyvale, California, US92001–2014
Yaakov, IL62010–2014
Yaskov, IL12010