LexDanaLexDanabeta
Inventor

Chih-Hsin Wang

Inventor
San Jose, CA, US

Overview

58→
Patents
2003–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 58 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices28%
H10DInorganic electric semiconductor devices27%
G11CStatic stores22%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
A01KAnimal husbandry2%
G06KGraphical data reading2%
H01QAntennas, i.e. radio aerials2%
H03KPulse technique2%
PatentTitleYear
11,092,244Sealing disc for vacuum closure20219,895,329'Formyl peptide receptor 1 antagonists and uses thereof'20188,792,274'Multi-level memory cell read, program, and erase techniques'20148,270,234'Positive and negative voltage level shifter circuit'20128,264,039'High-voltage LDMOSFET and applications therefor in standard CMOS'20128,248,848'System and methods for multi-level nonvolatile memory read, program and erase'20128,120,088'Non-volatile memory cell and array'20128,113,436'Semiconductor structure with communication element'20128,116,110'Array architecture including mirrored segments for nonvolatile memory device'20128,072,023'Isolation for non-volatile memory cell array'20117,948,810'Positive and negative voltage level shifter circuit'20117,847,374'Non-volatile memory cell array and logic'20107,824,981'Method and apparatus for semiconductor device and semiconductor memory device'20107,784,688'System for tracking elements using tags'20107,759,719'Electrically alterable memory cell'20107,746,704'Program-and-erase method for multilevel nonvolatile memory'20107,745,286'Methods of forming semiconductor devices'20107,741,177'Method and apparatus transporting charges in semiconductor device and semiconductor memory device'20107,724,596'Auto-zero current sensing amplifier'20107,719,050'Low power electrically alterable nonvolatile memory cells and arrays'20107,665,661'Secure system for tracking elements using tags'20107,626,864'Electrically alterable non-volatile memory cells and arrays'20097,613,041'Methods for operating semiconductor device and semiconductor memory device'20097,607,586'Semiconductor structure with RF element'20097,595,728'RF tags affixed in manufactured elements'20097,550,800'Method and apparatus transporting charges in semiconductor device and semiconductor memory device'20097,547,601'Low power electrically alterable nonvolatile memory cells and arrays'20097,411,244'Low power electrically alterable nonvolatile memory cells and arrays'20087,375,398'High voltage FET gate structure'20087,372,734'Methods of operating electrically alterable non-volatile memory cell'20087,297,634'Method and apparatus for semiconductor device and semiconductor memory device'20077,257,033'Inverter non-volatile memory cell and array system'20077,180,125'P-channel electrically alterable non-volatile memory cell'20077,144,778'Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line'20067,115,942'Method and apparatus for nonvolatile memory'20067,107,941'Safety device of collar for pet'20067,098,499'Electrically alterable non-volatile memory cell'20067,074,672'Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor'20067,018,897'Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate spacers'20067,015,102'Method of forming floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells made thereby'20066,958,513'Floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells'20056,952,033'Semiconductor memory array of floating gate memory cells with buried bit-line and raised source line'20056,917,069'Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor'20056,882,572'Method of operating a semiconductor memory array of floating gate memory cells with horizontally oriented edges'20056,868,015'Semiconductor memory array of floating gate memory cells with control gate spacer portions'20056,861,698'Array of floating gate memory cells having strap regions and a peripheral logic device region'20056,855,980'Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling'20056,773,989'Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate protruding portions'20046,773,974'Method of forming a semiconductor array of floating gate memory cells and strap regions'20046,756,633'Semiconductor memory array of floating gate memory cells with horizontally oriented floating gate edges'20046,743,674'Method of forming a semiconductor array of floating gate memory cells and strap regions, and a memory array and strap regions made thereby'20046,727,545'Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling'20046,695,101'Spooling apparatus'20046,627,942'Self-aligned floating gate poly for a flash E2PROM cell'20036,627,946'Semiconductor memory array of floating gate memory cells with control gates protruding portions'20036,580,642'Method of erasing nonvolatile tunneling injector memory cell'20036,566,706'Semiconductor array of floating gate memory cells and strap regions'20036,541,324'Method of forming a semiconductor array of floating gate memory cells having strap regions and a peripheral logic device region'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2006Patents assigned to SILICON STORAGE TECH INC (19)· patent assignee history
2003–2014Based in San Jose, CA, US· patent location history
2004–2006Based in Taichung, TW· patent location history
2005–2014Patents assigned to WANG CHIH-HSIN (24)· patent assignee history
2007–2010Patents assigned to MARVELL WORLD TRADE LTD (3)· patent assignee history
2010–2014Patents assigned to MARVELL INT LTD (8)· patent assignee history
2012–2014Patents assigned to TANG QIANG (4)· patent assignee history
2018Based in Kaohsiung, TW· patent location history
2021Based in Shanghai, CN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
WANG CHIH-HSINself242005–2014
SILICON STORAGE TECH INC192003–2006
MARVELL INT LTD82010–2014
TANG QIANG42012–2014
MARVELL WORLD TRADE LTD32007–2010
Locations
LocationPatentsSpan
San Jose, California, US542003–2014
Taichung, TW22004–2006
Shanghai, CN12021
Kaohsiung, TW12018