Inventor
Anup Bhalla
Inventor
Santa Clara, CA, US
Overview
Patents· 298 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices41%
H01LSemiconductor devices20%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H03KPulse technique2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
G01RMeasuring electric variables1%
Y10TTechnical subjects covered by former us classification1%
H10BElectronic memory devices0%
B82YSpecific uses or applications of nanostructures0%
PatentTitleYear
11,038,037Sawtooh electric field drift region structure for planar and trench power semiconductor devices202110,978,585MOS device with island region202110,896,968Device structure and manufacturing method using HDP deposited source-body implant block202110,825,733Reusable wide bandgap semiconductor substrate202010,763,351Vertical trench DMOSFET having integrated implants forming enhancement diodes in parallel with the body diode202010,686,062Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances202010,686,035Nano-tube MOSFET technology and devices202010,680,097MOSFET device and fabrication202010,593,759Nanotube semiconductor devices202010,573,762Vertical gallium nitride Schottky diode202010,535,764Device and fabrication of MOS device with island region202010,522,666Methods for fabricating anode shorted field stop insulated gate bipolar transistor201910,468,526Self-aligned slotted accumulation-mode field effect transistor (ACCUFET) structure and method201910,446,695Planar multi-implanted JFET201910,439,058Normally off gallium nitride field effect transistors (FET)201910,396,215Trench vertical JFET with improved threshold voltage control201910,396,158Termination structure for nanotube semiconductor devices201910,367,099Trench vertical JFET with ladder termination201910,367,098Vertical JFET made using a reduced masked set201910,333,006Termination structure for gallium nitride Schottky diode including junction barriar diodes201910,192,982Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact201910,177,221Integrated Schottky diode in high voltage semiconductor device201910,121,857Nano-tube MOSFET technology and devices201810,121,907Planar triple-implanted JFET201810,103,240Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode201810,074,742MOS device with island region201810,069,005Termination design for high voltage device201810,062,755Nanotube termination structure for power semiconductor devices201810,056,500Vertical JFET made using a reduced mask set201810,050,134Methods for fabricating anode shorted field stop insulated gate bipolar transistor201810,050,154Trench vertical JFET with ladder termination201810,038,106Termination structure for gallium nitride Schottky diode201810,032,584Robust semiconductor power devices with design to protect transistor cells with slower switching speed201810,020,389Normally off gallium nitride field effect transistors (FET)20189,978,740Uni-directional transient voltage suppressor (TVS)20189,960,237Termination structure with multiple embedded potential spreading capacitive structures for trench MOSFET20189,917,180'Trenched and implanted bipolar junction transistor'20189,911,840'Self aligned trench MOSFET with integrated diode'20189,899,474'Nanotube semiconductor devices'20189,882,049'Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method'20189,876,073Integrated Schottky diode in high voltage semiconductor device20189,866,213'High voltage switch module'20189,865,678'High voltage field balance metal oxide field effect transistor (FBM)'20189,806,175'Power MOSFET device structure for high frequency applications'20179,793,393'MOSFET device and fabrication'20179,748,375'Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact'20179,741,851'Trench junction barrier controlled Schottky'20179,728,655'Termination structure for gallium nitride schottky diode'20179,721,944'Hybrid wide-bandgap semiconductor bipolar switches'20179,716,057'Offset leadframe cascode package'20179,716,156'Device structure and manufacturing method using HDP deposited source-body implant block'20179,704,955'Nanotube semiconductor devices'20179,685,523'Diode structures with controlled injection efficiency for fast switching'20179,653,618'Planar triple-implanted JFET'20179,647,059'Manufacturing methods for accurately aligned and self-balanced superjunction devices'20179,620,498'Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection'20179,620,584'Integrated Schottky diode in high voltage semiconductor device'20179,577,072'Termination design for high voltage device'20179,570,404'Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application'20179,543,413'Corner layout for high voltage semiconductor devices'20179,520,464'Configuration and method to generate saddle junction electric field in edge termination'20169,520,480'Normally off gallium nitride field effect transistors (FET)'20169,502,503'Nanotube semiconductor devices'20169,478,646'Methods for fabricating anode shorted field stop insulated gate bipolar transistor'20169,466,710'Source and body contact structure for trench-DMOS devices using polysilicon'20169,455,249'Planar srfet using no additional masks and layout method'20169,450,083'High voltage field balance metal oxide field effect transistor (FBM)'20169,450,050'Lateral super junctions with high substrate breakdown and build in avalanche clamp diode'20169,443,928'Oxide terminated trench MOSFET with three or four masks'20169,412,684'Top exposed semiconductor chip package'20169,406,661'Protection circuit including vertical gallium nitride schottky diode and PN junction diode'20169,391,061'Uni-directional transient voltage suppressor (TVS)'20169,355,953'Vertical semiconductor MOSFET device with double substrate-side multiple electrode connections and encapsulation'20169,356,132'Integrating Schottky diode into power MOSFET'20169,349,796'Nanotube semiconductor devices'20169,331,068'Hybrid wide-bandgap semiconductor bipolar switches'20169,324,807'Silicon carbide MOSFET with integrated MOS diode'20169,324,858'Trench-gated MIS devices'20169,318,603'Method of making a low-Rdson vertical power MOSFET device'20169,312,336'MOSFET device with reduced breakdown voltage'20169,281,394'Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact'20169,257,375'Multi-die semiconductor package'20169,245,949'Nanotube semiconductor devices'20169,236,450'Fabrication of MOS device with schottky barrier controlling layer'20169,231,050'Configuration and method to generate saddle junction electric field in edge termination'20169,224,852'Corner layout for high voltage semiconductor devices'20159,219,003'Oxide terminated trench MOSFET with three or four masks'20159,214,544'Source and body contact structure for trench-DMOS devices using polysilicon'20159,171,917'Edge termination configurations for high voltage semiconductor power devices'20159,165,866'Stacked dual chip package having leveling projections'20159,148,139'Monolithically integrated cascode switches'20159,136,370'Shielded gate trench MOSFET package'20159,129,822'High voltage field balance metal oxide field effect transistor (FBM)'20159,093,286'Monolithic IGBT and diode structure for quai-resonant converters'20159,093,521'Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout'20159,087,911'Trench shield connected JFET'20159,083,343'Cascode switching circuit'20159,064,897'Termination design for high voltage device'20159,064,945'Normally off gallium nitride field effect transistors (FET)'20159,059,147'Junction barrier schottky (JBS) with floating islands'20159,029,236'Termination structure with multiple embedded potential spreading capacitive for trench MOSFET and method'20159,024,378'Device structure and manufacturing method using HDP deposited source-body implant block'20159,024,375'Nano-tube MOSFET technology and devices'20159,006,053'Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching'20159,000,481'Low capacitance transient voltage suppressor (TVS) with reduced clamping voltage'20158,994,140'Vertical gallium nitride Schottky diode'20158,980,716'Self aligned trench MOSFET with integrated diode'20158,975,720'Corner layout for superjunction device'20158,969,953'Method of forming a self-aligned charge balanced power DMOS'20158,963,233'Power MOSFET device structure for high frequency applications'20158,963,240'Shielded gate trench (SGT) mosfet devices and manufacturing processes'20158,956,940'Oxide terminated trench MOSFET with three or four masks'20158,946,942'Robust semiconductor power devices with design to protect transistor cells with slower switching speed'20158,933,550'Structure of mixed semiconductor encapsulation structure with multiple chips and capacitors'20158,933,506'Diode structures with controlled injection efficiency for fast switching'20158,933,549'Dual-leadframe multi-chip package'20158,928,079'MOS device with low injection diode'20158,928,031'Nanotube semiconductor devices'20158,927,402'Method for forming termination structure for gallium nitride Schottky diode'20158,900,949'Staggered column superjunction'20148,896,131'Cascode scheme for improved device switching behavior'20148,884,406'Etch depth determination structure'20148,878,292'Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method'20148,866,267'Semiconductor device with substrate-side exposed device-side electrode and method of fabrication'20148,860,098'Vjfet devices'20148,847,306'Direct contact in trench with three-mask shield gate process'20148,836,015'Planar SRFET using no additional masks and layout method'20148,835,977'TVS with low capacitance and forward voltage drop with depleted SCR as steering diode'20148,829,640'Configuration and method to generate saddle junction electric field in edge termination'20148,829,614'Integrated Schottky diode in high voltage semiconductor device'20148,829,603'Shielded gate trench MOSFET package'20148,828,857'Approach to integrate Schottky in MOSFET'20148,822,300'Low capacitance transient voltage suppressor (TVS) with reduced clamping voltage'20148,809,143'Fabrication of MOS device with schottky barrier controlling layer'20148,803,251'Termination of high voltage (HV) devices with new configurations and methods'20148,802,509'Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection'20148,802,530'MOSFET with improved performance through induced net charge region in thick bottom insulator'20148,785,270'Integrating schottky diode into power MOSFET'20148,785,279'High voltage field balance metal oxide field effect transistor (FBM)'20148,785,306'Manufacturing methods for accurately aligned and self-balanced superjunction devices'20148,785,278'Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact'20148,772,144'Vertical gallium nitride Schottky diode'20148,772,901'Termination structure for gallium nitride schottky diode'20148,759,908'Two-dimensional shielded gate transistor device and method of manufacture'20148,748,268'Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching'20148,728,890'Fabrication of MOS device with integrated Schottky diode in active region contact trench'20148,729,601'Nanotube semiconductor devices'20148,722,468'Semiconductor encapsulation method'20148,709,867'Dual-leadframe multi-chip package and method of manufacture'20148,709,893'Method of making a low-Rdson vertical power MOSFET device'20148,710,627'Uni-directional transient voltage suppressor (TVS)'20148,703,563'Source and body contact structure for trench-DMOS devices using polysilicon'20148,698,196'Low capacitance transient voltage suppressor (TVS) with reduced clamping voltage'20148,692,322'Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application'20148,680,643'Junction barrier Schottky (JBS) with floating islands'20148,680,613'Termination design for high voltage device'20148,643,135'Edge termination configurations for high voltage semiconductor power devices'20148,642,429'Wide and deep oxide trench in a semiconductor substrate with interspersed vertical oxide ribs'20148,643,071'Integrated snubber in a single poly MOSFET'20148,637,368'Fabrication of MOS device with varying trench depth'20148,637,926'Oxide terminated trench MOSFET with three or four masks'20148,598,623'Nanotube semiconductor devices and nanotube termination structures'20138,597,998'Power MOS device fabrication'20138,586,435'Fabrication of MOSFET device with reduced breakdown voltage'20138,586,414'Top exposed package and assembly method'20138,580,667'Self aligned trench MOSFET with integrated diode'20138,581,376'Stacked dual chip package and method of fabrication'20138,575,695'Lateral super junction device with high substrate-drain breakdown and built-in avalanche clamp diode'20138,575,685'Buried field ring field effect transistor (BUF-FET) integrated with cells implanted with hole supply path'20138,564,055'Shielded gate trench MOSFET device and fabrication'20138,557,671'Method for forming a transient voltage suppressor having symmetrical breakdown voltages'20138,519,476'Method of forming a self-aligned charge balanced power DMOS'20138,519,525'Semiconductor encapsulation and method thereof'20138,507,978'Split-gate structure in trench-based silicon carbide power device'20138,502,346'Monolithic IGBT and diode structure for quasi-resonant converters'20138,502,302'Integrating Schottky diode into power MOSFET'20138,497,160'Method for making solder-top enhanced semiconductor device of low parasitic packaging impedance'20138,482,048'Metal oxide semiconductor field effect transistor integrating a capacitor'20138,476,698'Corner layout for superjunction device'20138,471,332'Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout'20138,466,510'Staggered column superjunction'20138,450,794'MOS device with varying contact trench lengths'20138,445,370'Trench junction barrier controlled Schottky'20138,441,046'Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances'20138,431,470'Approach to integrate Schottky in MOSFET'20138,431,989'Shielded gate trench (SGT) MOSFET devices and manufacturing processes'20138,399,925'Termination structure with multiple embedded potential spreading capacitive structures for trench MOSFET and method'20138,390,058'Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions'20138,372,708'Device structure and manufacturing method using HDP deposited using deposited source-body implant block'20138,373,208'Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode'20138,367,501'Oxide terminated trench MOSFET with three or four masks'20138,362,552'MOSFET device with reduced breakdown voltage'20138,362,547'MOS device with Schottky barrier controlling layer'20138,362,585'Junction barrier Schottky diode with enforced upper contact structure and method for robust packaging'20138,357,973'Inverted-trench grounded-source FET structure with trenched source body short electrode'20138,354,316'Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection'20138,338,854'TVS with low capacitance and forward voltage drop with depleted SCR as steering diode'20128,338,860'Normally off gallium nitride field effect transistors (FET)'20128,324,053'High voltage MOSFET diode reverse recovery by minimizing P-body charges'20128,324,683'Oxide terminated trench MOSFET with three or four masks'20128,304,315'Integration of a sense FET into a discrete power MOSFET'20128,299,494'Nanotube semiconductor devices'20128,288,839'Transient voltage suppressor having symmetrical breakdown voltages'20128,288,229'Power MOS device fabrication'20128,283,723'MOS device with low injection diode'20128,283,212'Method of making a copper wire bond package'20128,283,213'Method of minimizing field stop insulated gate bipolar transistor (IGBT) buffer and emitter charge variation'20128,263,482'Nano-tube MOSFET technology and devices'20128,264,084'Solder-top enhanced semiconductor device for low parasitic impedance packaging'20128,253,192'MOS device with varying trench depth'20128,247,288'Method of integrating a MOSFET with a capacitor'20128,247,297'Method of filling large deep trench with high quality oxide for semiconductor devices'20128,247,329'Nanotube semiconductor devices'20128,236,651'Shielded gate trench MOSFET device and fabrication'20128,227,330'Junction barrier Schottky (JBS) with floating islands'20128,193,580'Shielded gate trench MOSFET device and fabrication'20128,187,939'Direct contact in trench with three-mask shield gate process'20128,178,954'Structure of mixed semiconductor encapsulation structure with multiple chips and capacitors'20128,174,283'Calibration technique for measuring gate resistance of power MOS gate device at wafer level'20128,169,062'Integrated circuit package for semiconductior devices with improved electric resistance and inductance'20128,164,199'Multi-die package'20128,163,618'Power MOSFET device structure for high frequency applications'20128,154,108'Dual-leadframe multi-chip package and method of manufacture'20128,148,256'Copper bonding method'20128,119,482'MOSFET using gate work function engineering for switching applications'20128,110,869'Planar SRFET using no additional masks and layout method'20128,110,472'High power and high temperature semiconductor power devices protected by non-uniform ballasted sources'20128,105,895'Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout'20128,093,651'MOS device with integrated schottky diode in active region contact trench'20128,067,822'Integrated circuit package for semiconductor devices with improved electric resistance and inductance'20118,058,727'Standing chip scale package'20118,053,891'Standing chip scale package'20118,053,298'Planar split-gate high-performance MOSFET structure and manufacturing method'20118,053,808'Layouts for multiple-stage ESD protection circuits for integrating with semiconductor power device'20118,049,315'Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package'20118,035,159'Device structure and manufacturing method using HDP deposited source-body implant block'20118,021,563'Etch depth determination for SGT technology'20118,008,747'High power and high temperature semiconductor power devices protected by non-uniform ballasted sources'20118,008,151'Shallow source MOSFET'20118,008,716'Inverted-trench grounded-source FET structure with trenched source body short electrode'20117,960,233'MOSFET with a second poly and an inter-poly dielectric layer over gate for synchronous rectification'20117,952,144'Integration of a sense FET into a discrete power MOSFET'20117,952,139'Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout'20117,948,029'MOS device with varying trench depth'20117,943,989'Nano-tube MOSFET technology and devices'20117,939,882'Integration of sense FET into discrete power MOSFET'20117,936,011'Shielded gate trench (SGT) MOSFET devices and manufacturing processes'20117,923,774'Power MOS device with conductive contact layer'20117,910,486'Method for forming nanotube semiconductor devices'20117,902,604'Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection'20117,884,454'Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package'20117,879,676'High density trench mosfet with single mask pre-defined gate and contact trenches'20117,875,541'Shallow source MOSFET'20117,868,381'Structures of and methods of fabricating trench-gated MIS devices'20117,863,675'MOSFET using gate work function engineering for switching applications'20117,825,431'Reduced mask configuration for power MOSFETs with electrostatic discharge (ESD) circuit protection'20107,800,169'Power MOS device'20107,799,646'Integration of a sense FET into a discrete power MOSFET'20107,795,108'Resistance-based etch depth determination for SGT technology'20107,786,531'MOSFET with a second poly and an inter-poly dielectric layer over gate for synchronous rectification'20107,767,526'High density trench MOSFET with single mask pre-defined gate and contact trenches'20107,764,105'MOSFET for synchronous rectification'20107,755,379'Configurations and method for carrying out wafer level unclamped inductive switching (UIS) tests'20107,745,878'Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact'20107,737,522'Trench junction barrier controlled Schottky device with top and bottom doped regions for enhancing forward current in a vertical direction'20107,671,662'Thermally stable semiconductor power device'20107,671,439'Junction barrier Schottky (JBS) with floating islands'20107,667,264'Shallow source MOSFET'20107,659,570'Power MOSFET device structure for high frequency applications'20107,633,119'Shielded gate trench (SGT) MOSFET devices and manufacturing processes'20097,633,140'Inverted J-lead for power devices'20097,605,425'Power MOS device'20097,598,620'Copper bonding compatible bond pad structure and method'20097,535,021'Calibration technique for measuring gate resistance of power MOS gate device at water level'20097,521,332'Resistance-based etch depth determination for SGT technology'20097,504,676'Planar split-gate high-performance MOSFET structure and manufacturing method'20097,453,119'Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact'20087,443,225'Thermally stable semiconductor power device'20087,436,022'Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout'20087,391,100'Integrated circuit package for semiconductor devices having a reduced leadframe pad and an increased bonding area'20087,378,884'MOSFET for synchronous rectification'20087,355,433'Configurations and method for carrying out wafer level unclamped inductive switching (UIS) tests'20087,335,946'Structures of and methods of fabricating trench-gated MIS devices'20087,285,822'Power MOS device'20077,221,195'MOSFET for synchronous rectification'20077,208,818'Power semiconductor package'20077,183,616'High speed switching MOSFETS using multi-parallel die packages with/without special leadframes'20077,122,882'Low cost power MOSFET with current monitoring'20067,005,347'Structures of and methods of fabricating trench-gated MIS devices'20066,841,852'Integrated circuit package for semiconductor devices with improved electric resistance and inductance'20056,838,722'Structures of and methods of fabricating trench-gated MIS devices'20056,437,419'Emitter ballast resistor with enhanced body effect to improve the short circuit withstand capability of power devices'20026,392,290'Vertical structure for semiconductor wafer-level chip scale packages'20026,285,060'Barrier accumulation-mode MOSFET'20016,275,093'IGBT gate drive circuit with short circuit protection'20016,080,614'Method of making a MOS-gated semiconductor device with a single diffusion'20005,894,141'Bipolar semiconductor power controlling devices with heterojunction'19995,872,028'Method of forming power semiconductor devices with controllable integrated buffer'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2001Based in Wilkes-Barre, PA, US· patent location history
2001–2021Based in Santa Clara, CA, US· patent location history
2006–2021Patents assigned to ALPHA & OMEGA SEMICONDUCTOR (257)· patent assignee history
2009–2021Patents assigned to BHALLA ANUP (132)· patent assignee history
2012–2019Patents assigned to BOBDE MADHUR (37)· patent assignee history
2012–2018Patents assigned to GUAN LINGPENG (30)· patent assignee history
2012–2018Patents assigned to YILMAZ HAMZA (28)· patent assignee history
2014–2020Based in Princeton Junction, NJ, US· patent location history
2018–2019Based in New Jersey, CA, US· patent location history
2018Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALPHA & OMEGA SEMICONDUCTOR | 257 | 2006–2021 |
| BHALLA ANUPself | 132 | 2009–2021 |
| BOBDE MADHUR | 37 | 2012–2019 |
| GUAN LINGPENG | 30 | 2012–2018 |
| YILMAZ HAMZA | 28 | 2012–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 263 | 2001–2021 |
| Princeton Junction, New Jersey, US | 26 | 2014–2020 |
| Wilkes-Barre, Pennsylvania, US | 4 | 1999–2001 |
| New Jersey, California, US | 2 | 2018–2019 |
| San Jose, California, US | 1 | 2018 |