Inventor
Arunangshu Kundu
Inventor
San Jose, CA, US
Overview
Patents· 31 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique54%
G06FElectric digital data processing31%
H10DInorganic electric semiconductor devices10%
G11CStatic stores5%
PatentTitleYear
9,147,025'Method for efficient FPGA packing'20157,941,685'Delay locked loop for an FPGA architecture'20117,886,130'Field programmable gate array and microcontroller system-on-a-chip'20117,579,869'Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks'20097,545,168'Clock tree network in a field programmable gate array'20097,516,303'Field programmable gate array and microcontroller system-on-a-chip'20097,484,113'Delay locked loop for an FPGA architecture'20097,432,733'Multi-level routing architecture in a field programmable gate array having transmitters and receivers'20087,394,289'Synchronous first-in/first-out block memory for a field programmable gate array'20087,385,420'Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks'20087,385,419'Dedicated input/output first in/first out module for a field programmable gate array'20087,375,553'Clock tree network in a field programmable gate array'20087,227,380'Synchronous first-in/first-out block memory for a field programmable gate array'20077,199,609'Dedicated input/output first in/first out module for a field programmable gate array'20077,171,575'Delay locked loop for and FPGA architecture'20077,126,374'Multi-level routing architecture in a field programmable gate array having transmitters and receivers'20067,102,385'Dedicated input/output first in/first out module for a field programmable gate array'20067,075,334'Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks'20067,069,419'Field programmable gate array and microcontroller system-on-a-chip'20067,049,846'Clock tree network in a field programmable gate array'20066,980,028'Dedicated input/output first in/first out module for a field programmable gate array'20056,980,027'Synchronous first-in/first-out block memory for a field programmable gate array'20056,976,185'Delay locked loop for an FPGA architecture'20056,946,871'Multi-level routing architecture in a field programmable gate array having transmitters and receivers'20056,891,396'Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks'20056,867,615'Dedicated input/output first in/first out module for a field programmable gate array'20056,838,902'Synchronous first-in/first-out block memory for a field programmable gate array'20056,825,690'Clock tree network in a field programmable gate array'20046,751,723'Field programmable gate array and microcontroller system-on-a-chip'20046,750,674'Carry chain for use between logic modules in a field programmable gate array'20046,718,477'Delay locked loop for an FPGA architecture'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2011Patents assigned to ACTEL CORP (29)· patent assignee history
2004–2015Based in San Jose, CA, US· patent location history
2015Patents assigned to MICROSEMI SOC CORP (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ACTEL CORP | 29 | 2004–2011 |
| MICROSEMI SOC CORP | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 31 | 2004–2015 |