Inventor

Jong-hyon Ahn

Inventor

Suwon-si, KR

Overview

1997–2010

Patent span

Electricity

Primary field (CPC H)

Patents· 33 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices30%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1027%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests11%

H10BElectronic memory devices4%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%

H05KPrinted circuits3%

B22DCasting of metals1%

F16LPipes1%

G11CStatic stores1%

PatentTitleYear

7,795,110'Trench isolation type semiconductor device which prevents a recess from being formed in a field region and method of fabricating the same'2010 7,709,340'Semiconductor integrated circuit device and method of manufacturing the same'2010 7,696,051'Method of fabricating a MOSFET having doped epitaxially grown source/drain region on recessed substrate'2010 7,585,734'Method of fabricating multi-gate transistor and multi-gate transistor fabricated thereby'2009 7,579,236'Nonvolatile memory device, method of fabricating and method of operating the same'2009 7,569,480'Semiconductor devices and methods of fabricating the same'2009 7,557,415'Trench isolation type semiconductor device and related method of manufacture'2009 7,544,991'Non-volatile memory device and methods of manufacturing and operating the same'2009 7,486,543'Asymmetrical SRAM device and method of manufacturing the same'2009 7,364,987'Method for manufacturing semiconductor device'2008 7,361,565'Method of forming a metal gate in a semiconductor device'2008 7,358,588'Trench isolation type semiconductor device which prevents a recess from being formed in a field region'2008 7,332,400'Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance'2008 7,288,848'Overlay mark for measuring and correcting alignment errors'2007 7,045,896'Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer'2006 7,008,835'Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance'2006 6,960,785'MOSFET and method of fabricating the same'2005 6,768,199'Flip chip type semiconductor device and method of fabricating the same'2004 6,765,255'Semiconductor device having metal-insulator-metal capacitor and fabrication method thereof'2004 6,764,910'Structure of semiconductor device and method for manufacturing the same'2004 6,555,462'Semiconductor device having stress reducing laminate and method for manufacturing the same'2003 6,552,438'Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same'2003 6,548,862'Structure of semiconductor device and method for manufacturing the same'2003 6,482,662'Semiconductor device fabricating method'2002 6,465,337'Methods of fabricating integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein'2002 6,335,567'Semiconductor device having stress reducing laminate and method for manufacturing the same'2002 6,300,233'Method of making a fuse in a semiconductor device'2001 6,285,540'Semiconductor device having a fuse'2001 6,232,189'Manufacturing method of semiconductor device'2001 6,175,145'Method of making a fuse in a semiconductor device and a semiconductor device having a fuse'2001 6,163,074'Integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein'2000 6,074,940'Method of making a fuse in a semiconductor device and a semiconductor device having a fuse'2000 5,612,246'Method for manufacturing semiconductor substrate having buck transistor and SOI transistor areas'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2010Patents assigned to SAMSUNG ELECTRONICS CO LTD (32)· patent assignee history

1997–2010Based in Suwon-si, KR· patent location history

2000–2010Based in Kyungki-do, KR· patent location history

2002Based in Kyonggi-do, KR· patent location history

2006–2008Based in Gyeonggi-do, KR· patent location history

2009Patents assigned to SAMSUNG ELECTRONCIS CO LTD (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SAMSUNG ELECTRONICS CO LTD	32	1997–2010
SAMSUNG ELECTRONCIS CO LTD	1	2009

Locations

Location	Patents	Span
Suwon-si, KR	21	1997–2010
Kyungki-do, KR	9	2000–2010
Gyeonggi-do, KR	2	2006–2008
Kyonggi-do, KR	1	2002