Inventor
Daniel C. Edelstein
Inventor
White Plains, NY, US
Overview
Patents· 297 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1032%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H01LSemiconductor devices16%
H10DInorganic electric semiconductor devices9%
Y10TTechnical subjects covered by former us classification4%
C23CCoating metallic material2%
H10BElectronic memory devices2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
H01CResistors2%
H10NElectric solid-state devices not otherwise provided for2%
PatentTitleYear
11,081,643Bevel metal removal using ion beam etch202111,056,425Structural enhancement of Cu nanowires202111,031,542Contact via with pillar of alternating layers202110,892,404Sacrificial buffer layer for metal removal at a bevel edge of a substrate202110,833,258MRAM device formation with in-situ encapsulation202010,777,735Contact via structures202010,770,347Interconnect structure202010,714,683Multilayer hardmask for high performance MRAM devices202010,686,124Contact via structures202010,680,169Multilayer hardmask for high performance MRAM devices202010,643,890Ultrathin multilayer metal alloy liner for nano Cu interconnects202010,615,074Advanced copper interconnects with hybrid microstructure202010,607,933Interconnect structures with fully aligned vias202010,593,591Interconnect structure202010,586,921Forming self-aligned contacts on pillar structures202010,586,920Forming self-aligned contacts on pillar structures202010,559,751Bottom electrode for semiconductor memory device202010,396,012Advanced through substrate via metallization in three dimensional semiconductor integration201910,396,013Advanced through substrate via metallization in three dimensional semiconductor integration201910,325,806Copper interconnect structure with manganese oxide barrier layer201910,325,978Resistors with controlled resistivity201910,312,181Advanced through substrate via metallization in three dimensional semiconductor integration201910,297,569Method of forming a three-dimensional bonded semiconductor structure having nitridized oxide regions201910,283,5833D resistor structure with controlled resistivity201910,276,649Metal resistors having nitridized dielectric surface layers and nitridized metal surface layers201910,276,435Advanced copper interconnects with hybrid microstructure201910,276,501Formation of liner and metal conductor201910,249,702Metal resistors having varying resistivity201910,249,703Metal resistors having nitridized metal surface layers with different nitrogen content201910,236,257Cobalt top layer advanced metallization for interconnects201910,224,241Copper interconnect structure with manganese oxide barrier layer201910,217,809Method of forming resistors with controlled resistivity201910,211,279Tunable resistor with curved resistor elements201910,211,148Structural enhancement of Cu nanowires201910,211,280Method of forming tunable resistor with curved resistor elements201910,204,856Interconnect structures with fully aligned vias201910,177,089Advanced E-fuse structure with controlled microstructure201910,177,092Formation of advanced interconnects201910,170,424Cobalt first layer advanced metallization for interconnects201910,163,793Cobalt first layer advanced metallization for interconnects201810,134,675Cobalt top layer advanced metallization for interconnects201810,128,186Simultaneous formation of liner and metal conductor201810,121,740Advanced e-Fuse structure with hybrid metal controlled microstructure201810,115,670Formation of advanced interconnects including set of metal conductor structures in patterned dielectric layer201810,109,585Formation of advanced interconnects including a set of metal conductor structures in a patterned dielectric layer201810,109,675Forming self-aligned contacts on pillar structures201810,032,716Advanced E-fuse structure with controlled microstructure201810,020,358Metal resistors having nitridized dielectric surface layers and nitridized metal surface layers201810,008,446Advanced E-fuse structure with enhanced electromigration fuse element20189,997,460Formation of advanced interconnects20189,991,330Resistors with controlled resistivity20189,985,088Metal resistors having nitridized metal surface layers with different nitrogen content20189,972,672Tunable resistor with curved resistor elements20189,972,671Metal resistors having varying resistivity20189,953,950Nitride-enriched oxide-to-oxide 3D wafer bonding20189,947,581Method of forming a copper based interconnect structure20189,947,6553D bonded semiconductor structure with an embedded capacitor20189,947,579Copper interconnect structure with manganese oxide barrier layer20189,947,622Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects20189,941,213Nitridized ruthenium layer for formation of cobalt interconnects20189,941,212Nitridized ruthenium layer for formation of cobalt interconnects20189,941,241Method for wafer-wafer bonding20189,911,690'Interconnect structures with fully aligned vias'20189,905,667'Lateral bipolar transistor'20189,893,012'Advanced e-fuse structure with hybrid metal controlled microstructure'20189,870,993'Simultaneous formation of liner and metal conductor'20189,859,155'Cobalt first layer advanced metallization for interconnects'20189,859,209'Advanced e-Fuse structure with enhanced electromigration fuse element'20189,859,215'Formation of advanced interconnects'20189,859,433'Cobalt top layer advanced metallization for interconnects'20189,852,990Cobalt first layer advanced metallization for interconnects20179,831,181Simultaneous formation of liner and metal conductor20179,824,917'Method and apparatus for single chamber treatment'20179,812,391'Advanced metallization for damage repair'20179,806,024'Simultaneous formation of liner and metal conductor'20179,799,605'Advanced copper interconnects with hybrid microstructure'20179,786,605'Advanced through substrate via metallization in three dimensional semiconductor integration'20179,773,737'Advanced metallization for damage repair'20179,761,529'Advanced metallization for damage repair'20179,728,399'Simultaneous formation of liner and metal conductor'20179,721,835'Modulating microstructure in interconnects'20179,721,788'Simultaneous formation of liner and metal conductor'20179,716,088'3D bonded semiconductor structure with an embedded capacitor'20179,716,063'Cobalt top layer advanced metallization for interconnects'20179,702,042'Method and apparatus for single chamber treatment'20179,691,705'Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects'20179,691,656'Self-forming embedded diffusion barriers'20179,659,817'Structure and process for W contacts'20179,653,567'Lateral bipolar transistor'20179,653,403'Structure and process for W contacts'20179,646,931'Formation of liner and metal conductor'20179,620,481'Substrate bonding with diffusion barrier structures'20179,620,479'3D bonded semiconductor structure with an embedded resistor'20179,601,371'Interconnect structure with barrier layer'20179,601,432'Advanced metallization for damage repair'20179,589,894'Copper interconnect structure and its formation'20179,583,410'Volumetric integrated circuit and volumetric integrated circuit manufacturing method'20179,536,780'Method and apparatus for single chamber treatment'20179,508,647'Single damascene interconnect structure'20169,496,239'Nitride-enriched oxide-to-oxide 3D wafer bonding'20169,472,503'Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects'20169,455,182'Interconnect structure with capping layer and barrier layer'20169,425,298'Lateral bipolar transistor'20169,406,617'Structure and process for W contacts'20169,332,628'Microelectronic structure including air gap'20169,324,650'Interconnect structures with fully aligned vias'20169,318,415'Beol structures incorporating active devices and mechanical strength'20169,299,765'Altering capacitance of MIM capacitor having reactive layer therein'20169,275,936'BEOL structures incorporating active devices and mechanical strength'20169,275,952'Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects'20169,245,794'Formation of alloy liner by reaction of diffusion barrier and seed layer for interconnect application'20169,224,686'Single damascene interconnect structure'20159,202,863'Structure with self aligned resist layer on an interconnect surface and method of making same'20159,190,321'Self-forming embedded diffusion barriers'20159,171,742'Alignment of integrated circuit chip stack'20159,105,693'Microelectronic structure including air gap'20159,099,468'Electronic fuse vias in interconnect structures'20159,070,686'Wiring switch designs based on a field effect device for reconfigurable interconnect paths'20159,064,874'Interconnect with titanium—oxide diffusion barrier'20159,064,937'Substrate bonding with diffusion barrier structures'20159,059,177'Doping of copper wiring structures in back end of line processing'20159,059,679'Tunable interconnect structures, and integrated circuit containing the same'20159,059,251'Microelectronic structure including air gap'20159,013,857'Altering capacitance of MIM capacitor having reactive layer therein'20158,986,921'Lithographic material stack including a metal-compound hard mask'20158,969,197'Copper interconnect structure and its formation'20158,927,421'Interconnect structures and methods of manufacturing of interconnect structures'20158,916,461'Electronic fuse vias in interconnect structures'20148,860,095'Interconnect wiring switches and integrated circuits including the same'20148,841,770'Semiconductor interconnect structure having enhanced performance and reliability'20148,772,942'Interconnect structure employing a Mn-group VIIIB alloy liner'20148,765,602'Doping of copper wiring structures in back end of line processing'20148,759,976'Structure with sub-lithographic random conductors as a physical unclonable function'20148,742,581'Enhanced diffusion barrier for interconnect structures'20148,716,134'Interconnect structure employing a Mn-group VIIIB alloy liner'20148,669,182'Metal cap with ultra-low κ dielectric material for circuit interconnect applications'20148,658,533'Semiconductor interconnect structure with multi-layered seed layer providing enhanced reliability and minimizing electromigration'20148,648,465'Semiconductor interconnect structure having enhanced performance and reliability'20148,624,323'BEOL structures incorporating active devices and mechanical strength'20148,617,984'Tungsten metallization: structure and fabrication of same'20138,610,276'Metal cap for back end of line (BEOL) interconnects, design structure and method of manufacture'20138,564,132'Tungsten metallization: structure and fabrication of same'20138,563,419'Method of manufacturing an interconnect structure and design structure thereof'20138,530,320'High-nitrogen content metal resistor and method of forming same'20138,525,169'Reliable physical unclonable function for device authentication'20138,513,769'Electrical fuses and resistors having sublithographic dimensions'20138,497,202'Interconnect structures and methods of manufacturing of interconnect structures'20138,497,580'Noble metal cap for interconnect structures'20138,492,289'Barrier layer formation for metal interconnects through enhanced impurity diffusion'20138,481,423'Methods to mitigate plasma damage in organosilicate dielectrics'20138,470,706'Methods to mitigate plasma damage in organosilicate dielectrics'20138,461,678'Structure with self aligned resist layer on an interconnect surface and method of making same'20138,440,522'Increasing an electrical resistance of a resistor by oxidation'20138,420,531'Enhanced diffusion barrier for interconnect structures'20138,404,145'Method for forming an indium cap layer'20138,383,507'Method for fabricating air gap interconnect structures'20138,363,379'Altering capacitance of MIM capacitor having reactive layer therein'20138,343,868'Device and methodology for reducing effective dielectric constant in semiconductor devices'20138,336,204'Formation of alloy liner by reaction of diffusion barrier and seed layer for interconnect application'20128,293,634'Structures and methods for improving solder bump connections in semiconductor devices'20128,294,270'Copper alloy via bottom liner'20128,288,268'Microelectronic structure including air gap'20128,247,904'Interconnection between sublithographic-pitched structures and lithographic-pitched structures'20128,232,645'Interconnect structures, design structure and method of manufacture'20128,227,336'Structure with self aligned resist layer on an interconnect surface and method of making same'20128,138,604'Metal cap with ultra-low k dielectric material for circuit interconnect applications'20128,133,810'Structure for metal cap applications'20128,129,286'Reducing effective dielectric constant in semiconductor devices'20128,120,179'Air gap interconnect structures and methods for forming the same'20128,120,143'Integrated circuit comb capacitor'20128,101,236'Method of fabricating a SiCOH dielectric material with improved toughness and improved Si-C bonding'20128,003,520'Air gap structure having protective metal silicide pads on a metal feature'20117,998,864'Noble metal cap for interconnect structures'20117,993,817'Structure with self aligned resist layer on an insulating surface and method of making same'20117,977,032'Method to create region specific exposure in a layer'20117,968,949'Contact forming method and related semiconductor device'20117,964,966'Via gouged interconnect structure and method of fabricating same'20117,955,971'Hybrid metallic wire and methods of fabricating same'20117,956,463'Large grain size conductive structure for narrow interconnect openings'20117,951,714'High aspect ratio electroplated metal feature and method'20117,951,708'Copper interconnect structure with amorphous tantalum iridium diffusion barrier'20117,943,480'Sub-lithographic dimensioned air gap formation and related structure'20117,928,569'Redundant barrier structure for interconnect and wiring applications, design structure and method of manufacture'20117,892,648'SiCOH dielectric material with improved toughness and improved Si-C bonding'20117,892,940'Device and methodology for reducing effective dielectric constant in semiconductor devices'20117,888,741'Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same'20117,884,477'Air gap structure having protective metal silicide pads on a metal feature'20117,863,150'Method to generate airgaps with a template first scheme and a self aligned blockout mask'20117,859,113'Structure including via having refractory metal collar at copper wire and dielectric layer liner-less interface and related method'20107,829,452'Terminal pad structures and methods of fabricating same'20107,829,427'Method of fabricating a high Q factor integrated circuit inductor'20107,804,391'Changing an electrical resistance of a resistor'20107,795,155'Method for forming an indium cap layer'20107,790,601'Forming interconnects with air gaps'20107,741,721'Electrical fuses and resistors having sublithographic dimensions'20107,727,890'High aspect ratio electroplated metal feature and method'20107,662,722'Air gap under on-chip passive device'20107,638,406'Method of fabricating a high Q factor integrated circuit inductor'2009RE040983'Method to plate C4 to copper stud'20097,615,482'Structure and method for porous SiCOH dielectric layers and adhesion promoting or etch stop layers having increased interfacial and mechanical strength'20097,592,685'Device and methodology for reducing effective dielectric constant in semiconductor devices'20097,585,722'Integrated circuit comb capacitor'20097,572,682'Semiconductor structure for fuse and anti-fuse applications'20097,566,653'Interconnect structure with grain growth promotion layer and method for forming the same'20097,531,444'Method to create air gaps using non-plasma processes to damage ILD materials'20097,528,048'Planar vertical resistor and bond pad resistor and related method'20097,517,736'Structure and method of chemically formed anchored metallic vias'20097,495,338'Metal capped copper interconnect'20097,494,912'Terminal pad structures and methods of fabricating same'20097,479,306'SiCOH dielectric material with improved toughness and improved Si-C bonding, semiconductor device containing the same, and method to make the same'20097,456,074'Increasing an electrical resistance of a resistor by nitridization'20087,405,147'Device and methodology for reducing effective dielectric constant in semiconductor devices'20087,394,110'Planar vertical resistor and bond pad resistor'20087,375,021'Method and structure for eliminating aluminum terminal pad material in semiconductor devices'20087,361,993'Terminal pad structures and methods of fabricating same'20087,351,639'Increasing an electrical resistance of a resistor by oxidation or nitridization'20087,327,033'Copper alloy via bottom liner'20087,276,787'Silicon chip carrier with conductive through-vias and method for fabricating same'20077,273,770'Compliant passivated edge seal for low-k interconnect structures'20077,271,699'Changing an electrical resistance of a resistor'20077,253,100'Reducing damage to ulk dielectric during cross-linked polymer removal'20077,129,561'Tri-metal and dual-metal stacked inductors'20067,119,018'Copper conductor'20067,115,996'Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped'20067,098,544'Edge seal for integrated circuit chips'20067,084,079'Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications'20067,081,680'Self-aligned corrosion stop for copper C4 and wirebond'20067,067,437'Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same'20067,068,138'High Q factor integrated circuit inductor'20067,033,927'Apparatus and method for thermal isolation, circuit cooling and electromagnetic shielding of a wafer'20067,030,031'Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material'20067,015,581'Low-K dielectric material system for IC application'20066,992,390'Liner with improved electromigration redundancy for damascene interconnects'20066,946,716'Electroplated interconnection structures on integrated circuit chips'20056,878,616'Low-k dielectric material system for IC application'20056,862,799'Method for changing an electrical resistance of a resistor'20056,784,088'Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped'20046,779,711'Self-aligned corrosion stop for copper C4 and wirebond'20046,777,809'BEOL decoupling capacitor'20046,746,947'Post-fuse blow corrosion prevention structure for copper fuses'20046,743,268'Chemical-mechanical planarization of barriers or liners for copper metallurgy'20046,740,539'Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates'20046,730,984'Increasing an electrical resistance of a resistor by oxidation or nitridization'20046,709,562'Method of making electroplated interconnection structures on integrated circuit chips'20046,649,531'Process for forming a damascene structure'20036,647,614'Method for changing an electrical resistance of a resistor'20036,646,345'Method for forming Co-W-P-Au films'20036,632,377'Chemical-mechanical planarization of metallurgy'20036,569,783'Graded composition diffusion barriers for chip wiring applications'20036,570,256'Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates'20036,551,931'Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped'20036,548,901'Cu/low-k BEOL with nonconcurrent hybrid dielectric interface'20036,531,412'Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications'20036,525,427'BEOL decoupling capacitor'20036,522,304'Dual damascene horn antenna'20036,498,385'Post-fuse blow corrosion prevention structure for copper fuses'20026,492,259'Process for making a planar integrated circuit interconnect'20026,486,557'Hybrid dielectric structure for improving the stiffness of back end of the line structures'20026,465,376'Method and structure for improving electromigration of chip interconnects'20026,457,234'Process for manufacturing self-aligned corrosion stop for copper C4 and wirebond'20026,437,440'Thin film metal barrier for electrical interconnections'20026,413,854'Method to build multi level structure'20026,399,496'Copper interconnection structure incorporating a metal seed layer'20026,375,693'Chemical-mechanical planarization of barriers or liners for copper metallurgy'20026,358,832'Method of forming barrier layers for damascene interconnects'20026,337,151'Graded composition diffusion barriers for chip wiring applications'20026,335,104'Method for preparing a conductive pad for electrical connection and conductive pad formed'20026,323,128'Method for forming Co-W-P-Au films'20016,301,903'Apparatus for activating fusible links on a circuit substrate'20016,297,140'Method to plate C4 to copper stud'20016,291,885'Thin metal barrier for electrical interconnections'20016,281,583'Planar integrated circuit interconnect'20016,270,646'Electroplating apparatus and method using a compressible contact'20016,251,787'Elimination of photo-induced electrochemical dissolution in chemical mechanical polishing'20016,251,528'Method to plate C4 to copper stud'20016,252,295'Adhesion of silicon carbide films'20016,234,870'Serial intelligent electro-chemical-mechanical wafer processor'20016,181,012'Copper interconnection structure incorporating a metal seed layer'20016,153,043'Elimination of photo-induced electrochemical dissolution in chemical mechanical polishing'20006,153,935'Dual etch stop/diffusion barrier for damascene interconnects'20006,133,136'Robust interconnect structure'20006,114,937'Integrated circuit spiral inductor'20006,106,687'Process and diffusion baffle to modulate the cross sectional distribution of flow rate and deposition rate'20006,103,096'Apparatus and method for the electrochemical etching of a wafer'20006,091,273'Voltage limiting circuit for fuse technology'20006,063,651'Method for activating fusible links on a circuit substrate'20006,054,329'Method of forming an integrated circuit spiral inductor with ferromagnetic liner'20005,999,037'Circuit for operating a control transistor from a fusible link'19995,952,674'Topography monitor'19995,884,990'Integrated circuit inductor'19995,793,272'Integrated circuit toroidal inductor'19985,679,269'Diamond-like carbon for use in VLSI and ULSI interconnect systems'19975,674,355'Diamond-like carbon for use in VLSI and ULSI interconnect systems'19975,559,367'Diamond-like carbon for use in VLSI and ULSI interconnect systems'19965,220,463'Optical delay line'19935,034,951'Femtosecond ultraviolet laser using ultra-thin beta barium borate'19915,017,806'Broadly tunable high repetition rate femtosecond optical parametric oscillator'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2021Based in White Plains, NY, US· patent location history
1991Based in Ithaca, NY, US· patent location history
1996–2021Patents assigned to IBM (285)· patent assignee history
1996–2006Based in New Rochelle, NY, US· patent location history
2010–2016Based in Yorktown Heights, NY, US· patent location history
2012–2016Patents assigned to EDELSTEIN DANIEL C (43)· patent assignee history
2012–2016Patents assigned to YANG CHIH-CHAO (12)· patent assignee history
2012–2016Patents assigned to NOGAMI TAKESHI (11)· patent assignee history
2012–2015Patents assigned to NITTA SATYANARAYANA V (9)· patent assignee history
2020Based in Armonk, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 285 | 1996–2021 |
| EDELSTEIN DANIEL Cself | 43 | 2012–2016 |
| YANG CHIH-CHAO | 12 | 2012–2016 |
| NOGAMI TAKESHI | 11 | 2012–2016 |
| NITTA SATYANARAYANA V | 9 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| White Plains, New York, US | 235 | 1991–2021 |
| New Rochelle, New York, US | 49 | 1996–2006 |
| Yorktown Heights, New York, US | 11 | 2010–2016 |
| Armonk, New York, US | 1 | 2020 |
| Ithaca, New York, US | 1 | 1991 |