Inventor
Andrea Sacco
Inventor
Alessandria, IT
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores79%
G05FSystems for regulating electric or magnetic variables13%
G01RMeasuring electric variables4%
H03KPulse technique4%
PatentTitleYear
7,983,098'Adaptive regulator for idle state in a charge pump circuit of a memory device'20117,599,231'Adaptive regulator for idle state in a charge pump circuit of a memory device'20097,551,498'Implementation of column redundancy for a flash memory with a high write parallelism'20097,447,071'Low voltage column decoder sharing a memory array p-well'20087,379,338'Method and system for regulating a program voltage value during multilevel memory device programming'20087,301,814'System and method for avoiding offset in and reducing the footprint of a non-volatile memory'20077,283,396'System and method for matching resistance in a non-volatile memory'20077,242,242'Fast dynamic low-voltage current mirror with compensated error'20077,236,050'Fast dynamic low-voltage current mirror with compensated error'20077,184,311'Method and system for regulating a program voltage value during multilevel memory device programming'20077,084,699'Fast dynamic low-voltage current mirror with compensated error'20066,954,102'Fast dynamic mirror sense amplifier with separate comparison equalization and evaluation paths'20056,873,551'Apparatus and method for a configurable mirror fast sense amplifier'20056,809,961'Regulation method for the drain, body and source terminals voltages in a non-volatile memory cell during a program phase and corresponding program circuit'20046,650,173'Programmable voltage generator'20036,603,681'Method of pulse programming, in particular for high-parallelism memory devices, and a memory device implementing the method'20036,504,758'Control circuit for a variable-voltage regulator of a nonvolatile memory with hierarchical row decoding'20036,456,150'Circuit for biasing a bulk terminal of a MOS transistor'20026,424,121'Voltage generator switching between alternating, first and second voltage values, in particular for programming multilevel cells'20026,373,780'Single supply voltage nonvolatile memory device with row decoding'20026,307,778'Non volatile memory with detection of short circuits between word lines'20016,259,635'Capacitive boosting circuit for the regulation of the word line reading voltage in non-volatile memories'20016,259,632'Capacitive compensation circuit for the regulation of the word line reading voltage in non-volatile memories'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2004Patents assigned to ST MICROELECTRONICS SRL (10)· patent assignee history
2001–2011Based in Alessandria, IT· patent location history
2005–2011Patents assigned to ATMEL CORP (13)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ATMEL CORP | 13 | 2005–2011 |
| ST MICROELECTRONICS SRL | 10 | 2001–2004 |
Locations
| Location | Patents | Span |
|---|---|---|
| Alessandria, IT | 23 | 2001–2011 |