Inventor

Philip Pan

Inventor

Fremont, CA, US

Overview

2002–2017

Patent span

Electricity

Primary field (CPC H)

Patents· 56 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary

H03KPulse technique45%

G11CStatic stores30%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses12%

G06FElectric digital data processing7%

G01RMeasuring electric variables4%

H04LTransmission of digital information, e.g. telegraphic communication1%

H05KPrinted circuits1%

PatentTitleYear

9,548,103'Scaleable look-up table based memory'2017 9,473,145'Programmable high-speed I/O interface'2016 9,166,589'Multiple data rate interface architecture'2015 9,123,437'Scaleable look-up table based memory'2015 8,829,948'Programmable high-speed I/O interface'2014 8,819,607'Method and apparatus to minimize clock tree skew in ICs'2014 8,644,100'Scaleable look-up table based memory'2014 8,593,195'High performance memory interface circuit architecture'2013 8,575,957'Multiple data rate interface architecture'2013 8,487,665'Programmable high-speed interface'2013 8,305,121'High-performance memory interface circuit architecture'2012 8,098,082'Multiple data rate interface architecture'2012 8,064,280'Scaleable look-up table based memory'2011 7,969,215'High-performance memory interface circuit architecture'2011 7,859,304'Multiple data rate interface architecture'2010 7,812,633'Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device'2010 7,768,430'Look-up table based memory'2010 7,725,755'Self-compensating delay chain for multiple-date-rate interfaces'2010 7,710,149'Input buffer for multiple differential I/O standards'2010 7,656,191'Distributed memory in field-programmable gate array integrated circuit devices'2010 7,586,341'Programmable high-speed interface'2009 7,535,275'High-performance memory interface circuit architecture'2009 7,487,415'Memory circuitry with data validation'2009 7,477,074'Multiple data rate interface architecture'2009 7,460,431'Implementation of double data rate embedded memory in programmable devices'2008 7,425,844'Input buffer for multiple differential I/O standards'2008 7,391,236'Distributed memory in field-programmable gate array integrated circuit devices'2008 7,321,518'Apparatus and methods for providing redundancy in integrated circuits'2008 7,315,188'Programmable high speed interface'2008 7,231,536'Control circuit for self-compensating delay chain for multiple-data-rate interfaces'2007 7,227,395'High-performance memory interface circuit architecture'2007 7,215,143'Input buffer for multiple differential I/O standards'2007 7,205,806'Loop circuitry with low-pass noise filter'2007 7,200,769'Self-compensating delay chain for multiple-date-rate interfaces'2007 7,167,023'Multiple data rate interface architecture'2007 7,119,579'Supply voltage detection circuit'2006 7,116,135'Programmable high speed I/O interface'2006 7,057,962'Address control for efficient memory partition'2006 7,002,384'Loop circuitry with low-pass noise filter'2006 6,992,947'Dual-port SRAM in a programmable logic device'2006 6,961,280'Techniques for implementing address recycling in memory circuits'2005 6,946,872'Multiple data rate interface architecture'2005 6,911,860'On/off reference voltage switch for multiple I/O standards'2005 6,912,164'Techniques for preloading data into memory on programmable circuits'2005 6,870,413'Schmitt trigger circuit with adjustable trip point voltages'2005 6,870,400'Supply voltage detection circuit'2005 6,825,692'Input buffer for multiple differential I/O standards'2004 6,825,698'Programmable high speed I/O interface'2004 6,806,733'Multiple data rate interface architecture'2004 6,766,505'Parallel programming of programmable logic using register chains'2004 6,747,903'Configurable decoder for addressing a memory'2004 6,731,137'Programmable, staged, bus hold and weak pull-up for bi-directional I/O'2004 6,714,044'Hi-speed parallel configuration of programmable logic'2004 6,661,733'Dual-port SRAM in a programmable logic device'2003 6,630,844'Supply voltage detection circuit'2003 6,433,579'Programmable logic integrated circuit devices with differential signaling capabilities'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2017Patents assigned to ALTERA CORP (56)· patent assignee history

2002–2017Based in Fremont, CA, US· patent location history

2003–2006Based in Freemont, CA, US· patent location history

2011–2014Patents assigned to PAN PHILIP (7)· patent assignee history

2012–2013Patents assigned to HUANG JOSEPH (5)· patent assignee history

2012–2013Patents assigned to SUNG CHIAKANG (5)· patent assignee history

2012–2013Patents assigned to CHONG YAN (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ALTERA CORP	56	2002–2017
PAN PHILIPself	7	2011–2014
HUANG JOSEPH	5	2012–2013
SUNG CHIAKANG	5	2012–2013
CHONG YAN	4	2012–2013

Locations

Location	Patents	Span
Fremont, California, US	51	2002–2017
Freemont, California, US	5	2003–2006