Inventor
PO-YU HUANG
Inventor
TW
Overview
Patents· 40 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices18%
H01LSemiconductor devices17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
B82YSpecific uses or applications of nanostructures11%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes5%
G06NComputing arrangements based on specific computational models4%
G06FElectric digital data processing3%
B65GTransport or storage devices, e.g. conveyors for loading or tipping, shop conveyor systems or pneumatic tube conveyors1%
C08GMacromolecular compounds obtained otherwise than by reactions only involving unsaturated carbon-to-carbon bonds1%
PatentTitleYear
12,550,407Semiconductor devices with backside via and methods thereof202612,486,111Electronic device and method for managing shelf configuration in warehouse202512,464,806Semiconductor transistor device having backside source/drain contact with a low-k spacer and method of forming the same202512,462,172Parameter optimization device and non-transitory computer readable medium202512,464,774Semiconductor structure and method for manufacturing the same202512,441,544Warehouse picking system and warehouse picking method202512,439,678Isolation structures202512,334,388Isolation structure and a self-aligned capping layer formed thereon202512,324,202Semiconductor device structure and method for forming the same202512,283,630Epitaxial source/drain structures for multigate devices and methods of fabricating thereof202512,278,188Different via configurations for different via interface requirements202512,266,606Semiconductor device with backside spacer and methods of forming the same202512,266,703Dielectric structures for semiconductor device structures202512,246,753Systems and methods for cooperative driving of connected autonomous vehicles in smart cities using responsibility-sensitive safety rules202512,224,324Method of forming backside power rails202512,142,565Different via configurations for different via interface requirements202412,118,653Depth analyzer and shading rate controller202412,080,769Contact structure with silicide and method for forming the same202412,068,378Semiconductor devices with backside via and methods thereof202412,068,200Backside via with a low-k spacer202412,057,392Conductive features having varying resistance202411,960,253System and method for parameter optimization with adaptive search space and user interface using the same202411,876,135Epitaxial source/drain structures for multigate devices and methods of fabricating thereof202411,855,154Vertical interconnect features and methods of forming202311,810,002Dynamic prediction model establishment method, electric device, and user interface202311,791,387Semiconductor devices with backside via and methods thereof202311,769,081Optimum sampling search system and method with risk assessment, and graphical user interface202311,728,394Method of forming backside power rails202311,721,626Semiconductor device with backside spacer and methods of forming the same202311,632,499Multi-camera positioning and dispatching system, and method thereof202311,615,987Backside via with a low-k spacer202311,606,278Packet information analysis method and network traffic monitoring device202311,551,155Ensemble learning predicting method and system202311,532,561Different via configurations for different via interface requirements202211,508,822Source/drain via having reduced resistance202211,319,410Precursor for polyimide and use thereof202211,276,643Semiconductor device with backside spacer and methods of forming the same202211,227,830Conductive features having varying resistance202211,198,792Method for preparing patterned coverlay on substrate202111,177,212Contact formation method and related structure2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (27)· patent assignee history
2021–2022Patents assigned to ETERNAL MAT CO LTD (2)· patent assignee history
2021–2026Based in TW· patent location history
2023–2025Patents assigned to IND TECH RES INST (8)· patent assignee history
2024Patents assigned to MEDIATEK INC (1)· patent assignee history
2025Patents assigned to UNIV ARIZONA STATE (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 27 | 2021–2026 |
| IND TECH RES INST | 8 | 2023–2025 |
| ETERNAL MAT CO LTD | 2 | 2021–2022 |
| MEDIATEK INC | 1 | 2024 |
| UNIV ARIZONA STATE | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 40 | 2021–2026 |