Inventor

Thomas Hughes

Inventor
San Francisco, CA, US

Overview

23→
Patents
2001–2019
Patent span
Physics
Primary field (CPC G)

Patents· 23 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

B01Lprimary
B01LChemical or physical laboratory apparatus for general use15%
G01NInvestigating or analysing materials by determining their chemical or physical properties15%
G11CStatic stores11%
B60GVehicle suspension arrangements5%
G02BOptical elements, systems or apparatus5%
G06FElectric digital data processing5%
G06KGraphical data reading5%
B41JTypewriters4%
Y10TTechnical subjects covered by former us classification4%
B41FPrinting machines or presses2%
PatentTitleYear
10,302,255Equipment comprising at least one hydropneumatic accumulator with automated maintenance201910,118,776Device and method for delivering a laboratory sample carrier from a stack of sample carriers20189,864,888'Histological sample tracking system'20189,636,929'Apparatus for marking a laboratory sample carrier'20178,952,787'Laboratory sample archiving apparatus and method'20158,811,528'Methods and apparatus for transmitting signals with selective delay for compensation of intersymbol interference and simultaneous switching outputs'20148,780,150'Method of making a laboratory slide'20148,773,484'Method and apparatus for marking a laboratory sample cassette'20148,651,045'Device and method for orientating a plurality of cassettes for laboratory samples'20148,390,925'Laboratory slide'20138,231,846'Identification tag with perforations for a laboratory sample cassette'20127,969,799'Multiple memory standard physical layer macro function'20117,944,460'Device and method for marking a cassette for laboratory samples'20117,858,391'Device and method for holding a cassette for laboratory samples'20107,839,716'Apparatus and systems for VT invariant DDR3 SDRAM write leveling'20107,818,528'System and method for asynchronous clock regeneration'20107,605,628'System for glitch-free delay updates of a standard cell-based programmable delay'20097,571,396'System and method for providing swap path voltage and temperature compensation'20097,454,303'System and method for compensating for PVT variation effects on the delay line of a clock signal'20087,405,984'System and method for providing programmable delay read data strobe gating with voltage and temperature compensation'20086,886,669'Method and device for actively suspending a wheel from a vehicle'20056,233,510'Method and system for predicting road profile'20016,186,257'Method and system for floating a vehicle'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2008–2014Patents assigned to LSI CORP (6)· patent assignee history
2008–2009Patents assigned to LSI LOGIC CORP (2)· patent assignee history
2008–2014Based in San Francisco, CA, US· patent location history
2010–2014Patents assigned to RAYMOND A LAMB LTD (5)· patent assignee history
2010–2014Based in Eastbourne, GB· patent location history
2012–2018Patents assigned to HUGHES THOMAS FERGUS (9)· patent assignee history
2014–2019Patents assigned to HUGHES THOMAS (2)· patent assignee history
2014–2018Based in Netherfield, GB· patent location history
2015Based in East Sussex, GB· patent location history
2019Based in Newry, IE· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
HUGHES THOMAS FERGUSself92012–2018
LSI CORP62008–2014
RAYMOND A LAMB LTD52010–2014
HUGHES THOMASself22014–2019
LSI LOGIC CORP22008–2009
Locations
LocationPatentsSpan
San Francisco, California, US82008–2014
Netherfield, GB52014–2018
Eastbourne, GB52010–2014
Newry, IE12019
East Sussex, GB12015