Inventor
Tom Choi
Inventor
Sunnyvale, CA, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1033%
H01LSemiconductor devices25%
H01JElectric discharge tubes or discharge lamps15%
H10DInorganic electric semiconductor devices8%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
B01DSeparation2%
B29CShaping or joining of plastics2%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form2%
Y10TTechnical subjects covered by former us classification2%
PatentTitleYear
10,770,269Apparatus and methods for reducing particles in semiconductor process chambers202010,629,473Footing removal for nitride spacer202010,600,639SiN spacer profile patterning202010,490,406Systems and methods for material breakthrough201910,424,487Atomic layer etching processes201910,403,507Shaped etch profile with oxidation201910,354,889Non-halogen etching of silicon-containing materials201910,062,575Poly directional etch by oxidation201810,026,621SiN spacer profile patterning20189,818,621'Cyclic oxide spacer etch process'20179,721,807'Cyclic spacer etching process with improved profile control'20179,478,433'Cyclic spacer etching process with improved profile control'20168,912,633'In-situ photoresist strip during plasma etching of active hard mask'20148,906,810'Pulsed dielectric etch process for in-situ metal hard mask shape control to enable void-free metallization'20148,283,255'In-situ photoresist strip during plasma etching of active hard mask'20128,124,516'Trilayer resist organic layer etch'20127,782,591'Methods of and apparatus for reducing amounts of particles on a wafer during wafer de-chucking'20107,479,457'Gas mixture for removing photoresist and post etch residue from low-k dielectric material and method of use thereof'20096,897,156'Vacuum plasma processor method'20056,531,029'Vacuum plasma processor apparatus and method'20036,514,378'Method for improving uniformity and reducing etch rate variation of etching polysilicon'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2014Patents assigned to LAM RES CORP (9)· patent assignee history
2003–2009Based in San Jose, CA, US· patent location history
2010–2014Based in Santa Clara, CA, US· patent location history
2012–2014Patents assigned to CHOI TOM (3)· patent assignee history
2012–2014Patents assigned to HAN TAEJOON (3)· patent assignee history
2012–2014Patents assigned to CHO SANGJUN (2)· patent assignee history
2014–2020Based in Sunnyvale, CA, US· patent location history
2016–2020Patents assigned to APPLIED MATERIALS INC (12)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLIED MATERIALS INC | 12 | 2016–2020 |
| LAM RES CORP | 9 | 2003–2014 |
| CHOI TOMself | 3 | 2012–2014 |
| HAN TAEJOON | 3 | 2012–2014 |
| CHO SANGJUN | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sunnyvale, California, US | 13 | 2014–2020 |
| Santa Clara, California, US | 4 | 2010–2014 |
| San Jose, California, US | 4 | 2003–2009 |