Inventor
Vijay Parthasarathy
Inventor
Mountain View, CA, US
Overview
Patents· 82 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices43%
A61BDiagnosis14%
H01LSemiconductor devices10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
G06TImage data processing or generation, in general5%
A61NElectrotherapy4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
A61MDevices for introducing media into, or onto, the body2%
G01SRadio direction-finding2%
G06FElectric digital data processing2%
PatentTitleYear
11,096,663Haptic feedback for ultrasound image acquisition202111,031,121System and method for indicating the quality of information to support decision making202111,007,382Real time dosimetry of ultrasound imaging probe202111,006,923Ultrasonically guided biopsies in three dimensions202110,966,629Virtually-oriented electromagnetic tracking coil for catheter based navigation202110,964,694Multi-transistor device including first and second LDMOS transistors having respective drift regions separated in a thickness direction by a shared RESURF layer202110,898,728Adaptive treatment planning for hyperthermia-enhanced radiation therapy202110,833,164LDMOS transistors and associated systems and methods202010,702,248Ultrasound acquisition feedback guidance to a target view202010,667,673Handheld catheter driver with endoscope mount utilizing friction-driven wheel mechanism202010,646,279Imaging apparatus for brachytherapy or biopsy202010,561,818Pre-curved steerable catheter with pull-wires for dexterous deflection control202010,405,838Side-looking lung biopsy device201910,404,976Intra-operative quality monitoring of tracking systems201910,376,179MPR slice selection for visualization of catheter in three-dimensional ultrasound201910,299,684User interface for photonic tools and electromagnetic tracking guided bronchoscope201910,269,916LDMOS transistors and associated systems and methods201910,251,627Elastography measurement system and method201910,199,475LDMOS transistors and associated systems and methods201910,123,767Ultrasonic guidance of multiple invasive devices in three dimensions201810,080,910Real-time adaptive dose computation radiation therapy20189,993,304Visualization of catheter of three-dimensional ultrasound20189,972,681High voltage vertical semiconductor device with multiple pillars in a racetrack arrangement20189,768,274'Laterally-graded doping of materials'20179,717,481'Method of adjusting focal zone in ultrasound-guided procedures by tracking an electromagnetic sensor that implemented on a surgical device'20179,660,053'High-voltage field-effect transistor having multiple implanted layers'20179,607,381'Accurate and rapid mapping of points from ultrasound images to tracking systems'20179,601,613'Gate pullback at ends of high-voltage vertical transistor structure'20179,478,028'Intelligent landmark selection to improve registration accuracy in multimodal image fusion'20169,472,630'Deposit/etch for tapered oxide'20169,263,564'Power integrated circuit with incorporated sense FET'20169,259,155'Method to estimate interfractional and intrafractional organ motion for adaptive external beam radiotherapy'20169,196,681'Metal oxide semiconductor field effect transistor with reduced surface field folding'20159,196,680'Metal oxide semiconductor field effect transistor with reduced surface field folding'20158,866,201'High-voltage transistor device with integrated resistor'20148,823,093'High-voltage transistor structure with reduced gate capacitance'20148,816,433'Checkerboarded high-voltage vertical transistor layout'20148,765,609'Deposit/etch for tapered oxide'20148,742,495'High-voltage vertical transistor with a varied width silicon pillar'20148,653,583'Sensing FET integrated with a high-voltage transistor'20148,653,600'High-voltage monolithic schottky device structure'20148,552,493'Segmented pillar layout for a high-voltage vertical transistor'20138,426,915'Power integrated circuit device with incorporated sense FET'20138,410,551'Checkerboarded high-voltage vertical transistor layout'20138,410,548'Method of fabricating a deep trench insulated gate bipolar transistor'20138,399,907'VTS insulated gate bipolar transistor'20138,395,207'High-voltage vertical transistor with a varied width silicon pillar'20138,247,287'Method of fabricating a deep trench insulated gate bipolar transistor'20128,222,691'Gate pullback at ends of high-voltage vertical transistor structure'20128,207,580'Power integrated circuit device with incorporated sense FET'20128,207,577'High-voltage transistor structure with reduced gate capacitance'20128,129,815'High-voltage transistor device with integrated resistor'20128,093,621'VTS insulated gate bipolar transistor'20128,076,723'Method of fabricating a deep trench insulated gate bipolar transistor'20118,022,456'Checkerboarded high-voltage vertical transistor layout'20117,964,912'High-voltage vertical transistor with a varied width silicon pillar'20117,871,882'Method of fabricating a deep trench insulated gate bipolar transistor'20117,859,037'Checkerboarded high-voltage vertical transistor layout'20107,816,731'Segmented pillar layout for a high-voltage vertical transistor'20107,732,860'Gate metal routing for transistor with checkerboarded layout'20107,595,523'Gate pullback at ends of high-voltage vertical transistor structure'20097,557,406'Segmented pillar layout for a high-voltage vertical transistor'20097,476,593'Semiconductor device and method of forming the same'20097,468,536'Gate metal routing for transistor with checkerboarded layout'20087,368,786'Process insensitive ESD protection device'20087,355,260'Schottky device and method of forming'20087,309,638'Method of manufacturing a semiconductor component'20077,282,386'Schottky device and method of forming'20077,247,003'Stacked lamellate assembly'20077,141,860'LDMOS transistor'20067,095,092'Semiconductor device and method of forming the same'20067,071,518'Schottky device'20066,933,546'Semiconductor component'20056,930,027'Method of manufacturing a semiconductor component'20056,882,023'Floating resurf LDMOSFET and method of manufacturing same'20056,815,780'Semiconductor component with substrate injection protection structure'20046,734,524'Electronic component and method of manufacturing same'20046,703,895'Semiconductor component and method of operating same'20046,693,339'Semiconductor component and method of manufacturing same'20046,573,562'Semiconductor component and method of operation'20036,528,849'Dual-gate resurf superjunction lateral DMOSFET'20036,110,804'Method of fabricating a semiconductor device having a floating field conductor'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2009Based in Phoenix, AZ, US· patent location history
2005–2009Patents assigned to FREESCALE SEMICONDUCTOR INC (10)· patent assignee history
2007–2017Based in Palo Alto, CA, US· patent location history
2008–2018Patents assigned to POWER INTEGRATIONS INC (35)· patent assignee history
2011–2019Patents assigned to PARTHASARATHY VIJAY (22)· patent assignee history
2011–2014Patents assigned to BANERJEE SUJIT (15)· patent assignee history
2011–2016Based in Mountain View, CA, US· patent location history
2014–2021Based in Sunnyvale, CA, US· patent location history
2016–2021Patents assigned to KONINKLIJKE PHILIPS NV (21)· patent assignee history
2017–2021Based in Mount Kisco, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| POWER INTEGRATIONS INC | 35 | 2008–2018 |
| PARTHASARATHY VIJAYself | 22 | 2011–2019 |
| KONINKLIJKE PHILIPS NV | 21 | 2016–2021 |
| BANERJEE SUJIT | 15 | 2011–2014 |
| FREESCALE SEMICONDUCTOR INC | 10 | 2005–2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| Mountain View, California, US | 22 | 2011–2016 |
| Phoenix, AZ, US | 16 | 2003–2009 |
| Sunnyvale, California, US | 11 | 2014–2021 |
| Palo Alto, California, US | 9 | 2007–2017 |
| Mount Kisco, New York, US | 8 | 2017–2021 |