Inventor
Dung Q. Nguyen
Inventor
US
Overview
Patents· 39 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing95%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
PatentTitleYear
12,204,902Routing instruction results to a register block of a subdivided register file based on register block utilization rate202511,995,445Assignment of microprocessor register tags at issue time202411,941,398Fast mapper restore for flush in processor202411,900,116Loosely-coupled slice target file data202411,886,883Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction202411,868,773Inferring future value for speculative branch resolution in a microprocessor202411,768,684Compaction of architected registers in a simultaneous multithreading processor202311,755,325Instruction handling for accumulation of register results in a microprocessor202311,748,104Microprocessor that fuses load and compare instructions202311,709,676Inferring future value for speculative branch resolution202311,663,013Dependency skipping execution202311,635,961Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file202311,561,794Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry202311,561,798On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer202311,537,402Execution elision of intermediate instruction by processor202211,531,548Fast perfect issue of dependent instructions in a distributed issue queue system202211,500,642Assignment of microprocessor register tags at issue time202211,403,109Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor202211,392,386Program counter (PC)-relative load and store addressing for fused instructions202211,366,671Completion mechanism for a microprocessor instruction completion table202211,360,775Slice-based allocation history buffer202211,360,779Logical register recovery within a processor202211,327,757Processor providing intelligent management of values buffered in overlaid architected and non-architected register files202211,327,766Instruction dispatch routing202211,301,254Instruction streaming using state migration202211,269,647Finish status reporting for a simultaneous multithreading processor using an instruction completion table202211,256,507Thread transition management202211,249,757Handling and fusing load instructions in a processor202211,194,578Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor202111,188,340Multiple streams execution for hard-to-predict branches in a microprocessor202111,188,332System and handling of register data in processors202111,182,164Pairing issue queues for complex instructions and instruction fusion202111,163,568Implementing write ports in register-file array cell202111,157,276Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entry202111,150,909Energy efficient source operand issue202111,144,364Supporting speculative microprocessor instruction execution202111,144,323Independent mapping of threads202111,144,319Redistribution of architected states for a processor register file202111,138,050Operation of a multi-slice processor implementing a hardware level transfer of an execution thread2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to IBM (39)· patent assignee history
2021–2025Based in US· patent location history
2022Patents assigned to INT BUSINES MACHINES CORPORATION (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 39 | 2021–2025 |
| INT BUSINES MACHINES CORPORATION | 1 | 2022 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 39 | 2021–2025 |