Inventor
Ute Gaertner
Inventor
Schoenaich, DE
Overview
Patents· 51 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing81%
H04LTransmission of digital information, e.g. telegraphic communication10%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
E03BInstallations or methods for obtaining, collecting, or distributing water2%
G01FMeasuring volume, volume flow, mass flow or liquid level2%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes2%
PatentTitleYear
11,036,647Suspending translation look-aside buffer purge execution in a multi-processor environment202110,929,312Zone-SDID mapping scheme for TLB purges202110,698,835Suspending translation look-aside buffer purge execution in a multi-processor environment202010,423,330Data collection in a multi-threaded processor201910,387,311Cache directory that determines current state of a translation in a microprocessor core cache201910,353,828Zone-SDID mapping scheme for TLB purges201910,353,825Suspending translation look-aside buffer purge execution in a multi-processor environment201910,353,827Zone-SDID mapping scheme for TLB purges201910,248,575Suspending translation look-aside buffer purge execution in a multi-processor environment201910,176,002Quiesce handling in multithreaded environments201910,102,152Protecting a memory from unauthorized access201810,102,151Protecting a memory from unauthorized access201810,025,608Quiesce handling in multithreaded environments201810,013,279Processing interrupt requests201810,002,022Processing interrupt requests20189,798,678'Protecting storage from unauthorized access'20179,779,032'Protecting storage from unauthorized access'20179,772,954'Protecting contents of storage'20179,715,462'Protecting contents of storage'20179,697,135'Suppressing virtual address translation utilizing bits and instruction tagging'20179,678,830'Recovery improvement for quiesced systems'20179,665,424'Recovery improvement for quiesced systems'20179,596,076'Encrypted data exchange between computer systems'20179,432,183'Encrypted data exchange between computer systems'20169,372,805'Operating on translation look-aside buffers in a multiprocessor environment'20169,330,017'Suppressing virtual address translation utilizing bits and instruction tagging'20169,330,018'Suppressing virtual address translation utilizing bits and instruction tagging'20169,274,957'Monitoring a value in storage without repeated storage access'20169,218,288'Monitoring a value in storage without repeated storage access'20159,092,382'Reducing microprocessor performance loss due to translation table coherency in a multi-processor system'20159,069,715'Reducing microprocessor performance loss due to translation table coherency in a multi-processor system'20158,966,221'Translating translation requests having associated priorities'20158,572,624'Providing multiple quiesce state machines in a computing environment'20138,458,438'System, method and computer program product for providing quiesce filtering for shared memory'20138,407,701'Facilitating quiesce operations within a logically partitioned computer system'20138,332,614'System, method and computer program product for providing a programmable quiesce filtering register'20128,234,642'Filtering processor requests based on identifiers'20128,166,239'Translation lookaside buffer and related method and program product utilized for virtual addresses'20128,151,085'Method for address translation in virtual machines'20128,140,834'System, method and computer program product for providing a programmable quiesce filtering register'20127,530,067'Filtering processor requests based on identifiers'20097,401,185'Buffered indexing to manage hierarchical tables'20087,020,761'Blocking processing restrictions based on page indices'20066,996,698'Blocking processing restrictions based on addresses'20066,766,434'Method for sharing a translation lookaside buffer between CPUs'20046,418,522'Translation lookaside buffer for virtual memory systems'20026,237,076'Method for register renaming by copying a 32 bits instruction directly or indirectly to a 64 bits instruction'20016,108,771'Register renaming with a pool of physical registers'20005,996,063'Management of both renamed and architected registers in a superscalar computer system'19995,978,957'Very fast pipelined shifter element with parity prediction'19995,761,734'Token-based serialisation of instructions in a multiprocessor system'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2021Patents assigned to IBM (51)· patent assignee history
1998–2021Based in Schoenaich, DE· patent location history
1999–2001Based in Schonaich, DE· patent location history
2008Based in Baden-Wurttemberg, DE· patent location history
2009–2012Based in Baden-Baden, DE· patent location history
2012–2015Patents assigned to GAERTNER UTE (10)· patent assignee history
2012–2013Patents assigned to HELLER LISA C (6)· patent assignee history
2012–2015Patents assigned to SLEGEL TIMOTHY J (4)· patent assignee history
2012–2013Patents assigned to NAVARRO JENNIFER A (3)· patent assignee history
2019Based in Boeblingen, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 51 | 1998–2021 |
| GAERTNER UTEself | 10 | 2012–2015 |
| HELLER LISA C | 6 | 2012–2013 |
| SLEGEL TIMOTHY J | 4 | 2012–2015 |
| NAVARRO JENNIFER A | 3 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Schoenaich, DE | 43 | 1998–2021 |
| Schonaich, DE | 4 | 1999–2001 |
| Baden-Baden, DE | 2 | 2009–2012 |
| Boeblingen, DE | 1 | 2019 |
| Baden-Wurttemberg, DE | 1 | 2008 |