Inventor
THOMAS A. VOLPE
Inventor
US
Overview
Patents· 39 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing55%
G06NComputing arrangements based on specific computational models25%
H04LTransmission of digital information, e.g. telegraphic communication12%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
G11CStatic stores2%
H01LSemiconductor devices2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
12,530,227Monitoring a software-based activity monitor that configures the throttling of a hardware-based activity monitor202612,517,700Systolic array with output rounding for multiple source/destination data type pairs202612,423,058Systolic array with input reduction to multiple reduced inputs202512,333,274Data-type-aware clock-gating202512,210,940On-circuit activity monitoring for modifying integrated circuit processing202512,197,308On-circuit utilization monitoring for a systolic array202512,182,064Multiple accumulate busses in a systolic array202412,137,049Extending virtual routing and forwarding202412,132,028Semiconductor package with capacitance die202412,067,492Processing for multiple input data sets in a multi-layer neural network202412,008,466Processor with control flow202411,907,144Early semaphore update202411,900,024Simulating network packets in a packet processing pipeline202411,899,551On-chip software-based activity monitor to configure throttling at a hardware-based activity monitor202411,880,682Systolic array with efficient input reduction and extended array performance202411,848,849Testing computer networks in real time202311,816,446Systolic array component combining multiple integer and floating-point data types202311,797,853Processing for multiple input data sets202311,762,803Multiple accumulate busses in a systolic array202311,729,300Generating programmatically defined fields of metadata for network packets202311,546,336Independently configurable access device stages for processing interconnect access requests202311,528,187Dynamically configurable networking device interfaces for directional capacity modifications202211,520,731Arbitrating throttling recommendations for a systolic array202211,487,675Collecting statistics for persistent memory202211,475,306Processing for multiple input data sets202211,467,983Independently configurable interleaving for interconnect access requests202211,461,631Scheduling neural network computations based on memory capacity202211,442,890On-circuit data activity monitoring for a systolic array202211,422,773Multiple busses within a systolic array processing element202211,416,749Execution synchronization and tracking202211,392,406Alternative interrupt reporting channels for microcontroller access devices202211,347,916Increasing positive clock skew for systolic array critical path202211,321,179Powering-down or rebooting a device in a system fabric202211,314,635Tracking persistent memory usage202211,308,026Multiple busses interleaved in a systolic array202211,308,027Multiple accumulate busses in a systolic array202211,281,967Event-based device performance monitoring202211,232,062Parallelism within a systolic array using multiple accumulate busses202211,175,839Independently configurable remapping for interconnect access requests2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to AMAZON TECH INC (39)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| AMAZON TECH INC | 39 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 39 | 2021–2026 |