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Inventor

Sudip K. Nag

Inventor
San Jose, CA, US

Overview

33→
Patents
1997–2016
Patent span
Physics
Primary field (CPC G)

Patents· 33 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing76%
H03KPulse technique16%
H10DInorganic electric semiconductor devices5%
G01RMeasuring electric variables3%
PatentTitleYear
9,405,871'Determination of path delays in circuit designs'20168,448,122'Implementing sub-circuits with predictable behavior within a circuit design'20137,728,623'Programmable logic cells with local connections'20107,725,868'Method and apparatus for facilitating signal routing within a programmable logic device'20107,605,605'Programmable logic cells with local connections'20097,428,722'Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes'20087,398,496'Unified placer infrastructure'20087,358,761'Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes'20087,306,977'Method and apparatus for facilitating signal routing within a programmable logic device'20077,240,315'Automated local clock placement for FPGA designs'20077,143,380'Method for application of network flow techniques under constraints'20067,143,378'Method and apparatus for timing characterization of integrated circuit designs'20067,076,758'Using router feedback for placement improvements for logic design'20067,072,815'Relocation of components for post-placement optimization'20067,051,312'Upper-bound calculation for placed circuit design performance'20066,983,439'Unified placer infrastructure'20066,877,040'Method and apparatus for testing routability'20056,857,115'Placement of objects with partial shape restriction'20056,789,244'Placement of clock objects under constraints'20046,766,504'Interconnect routing using logic levels'20046,732,349'Method and apparatus for improving PIP coverage in programmable logic devices'20046,711,600'System and method for RAM-partitioning to exploit parallelism of RADIX-2 elements in FPGAs'20046,625,795'Method and apparatus for placement of input-output design objects into a programmable gate array'20036,507,860'System and method for RAM-partitioning to exploit parallelism of RADIX-2 elements in FPGAs'20036,484,298'Method and apparatus for automatic timing-driven implementation of a circuit design'20026,415,425'Method for analytical placement of cells using density surface representations'20026,317,768'System and method for RAM-partitioning to exploit parallelism of RADIX-2 elements in FPGAs'20016,289,496'Placement of input-output design objects into a programmable gate array supporting multiple voltage standards'20016,167,416'System and method for RAM-partitioning to exploit parallelism of radix-2 elements in FPGAS'20006,099,583'Core-based placement and annealing methods for programmable logic devices'20006,086,631'Post-placement residual overlap removal method for core-based PLD programming process'20006,021,423'Method for parallel-efficient configuring an FPGA for large FFTS and other vector rotation computations'20005,598,343'Method of segmenting an FPGA channel architecture for maximum routability and performance'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997Based in Pittsburgh, PA, US· patent location history
2000–2016Patents assigned to XILINX INC (28)· patent assignee history
2000–2016Based in San Jose, CA, US· patent location history
2008–2009Patents assigned to CSWITCH CORP (2)· patent assignee history
2010Patents assigned to AGATE LOGIC INC (1)· patent assignee history
2013Patents assigned to AGGARWAL RAJAT (1)· patent assignee history
2013Patents assigned to ARSLAN HASAN (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
XILINX INC282000–2016
CSWITCH CORP22008–2009
AGATE LOGIC INC12010
AGGARWAL RAJAT12013
ARSLAN HASAN12013
Locations
LocationPatentsSpan
San Jose, California, US322000–2016
Pittsburgh, Pennsylvania, US11997