Inventor
Pei-Yuan Gao
Inventor
San Jose, CA, US
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1038%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
H10BElectronic memory devices16%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests11%
C23CCoating metallic material8%
H10DInorganic electric semiconductor devices8%
PatentTitleYear
8,202,810'Low-H plasma treatment with N2 anneal for electronic memory devices'20127,300,886'Interlayer dielectric for charge loss improvement'20077,297,592'Semiconductor memory with data retention liner'20077,183,198'Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes'20077,060,554'PECVD silicon-rich oxide layer for reduced UV charging'20067,033,960'Multi-chamber deposition of silicon oxynitride film for patterning'20067,023,046'Undoped oxide liner/BPSG for improved data retention'20066,803,313'Method for forming a hardmask employing multiple independently formed layers of a pecvd material to reduce pinholes'20046,803,265'Liner for semiconductor memories and manufacturing method therefor'20046,764,949'Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication'20046,653,735'CVD silicon carbide layer as a BARC and hard mask for gate patterning'20036,627,973'Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device'20036,489,253'Method of forming a void-free interlayer dielectric (ILD0) for 0.18-m flash memory technology and semiconductor device thereby formed'20026,410,461'Method of depositing sion with reduced defects'20026,403,385'Method of inspecting a semiconductor wafer for defects'20026,369,453'Semiconductor wafer for measurement and recordation of impurities in semiconductor insulators'20026,297,065'Method to rework device with faulty metal stack layer'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2007Patents assigned to ADVANCED MICRO DEVICES INC (14)· patent assignee history
2001–2012Based in San Jose, CA, US· patent location history
2004Patents assigned to FASL LLC (1)· patent assignee history
2007–2012Patents assigned to SPANSION LLC (3)· patent assignee history
2012Patents assigned to BRENNAN WILLIAM S (1)· patent assignee history
2012Patents assigned to EVANS ALLEN L (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 14 | 2001–2007 |
| SPANSION LLC | 3 | 2007–2012 |
| BRENNAN WILLIAM S | 1 | 2012 |
| EVANS ALLEN L | 1 | 2012 |
| FASL LLC | 1 | 2004 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 17 | 2001–2012 |