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Inventor

Leo Mathew

Inventor
Austin, TX, US

Overview

62→
Patents
1999–2014
Patent span
Electricity
Primary field (CPC H)

Patents· 62 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices40%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H10BElectronic memory devices10%
B82YSpecific uses or applications of nanostructures7%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
G11CStatic stores4%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation4%
H10HInorganic light-emitting semiconductor devices having potential barriers3%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution3%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light2%
PatentTitleYear
8,643,066'Multiple device types including an inverted-T channel transistor and method therefor'20148,575,588'Phase change memory cell with heater and method therefor'20138,563,355'Method of making a phase change memory cell having a silicide heater in conjunction with a FinFET'20138,513,066'Method of making an inverted-T channel transistor'20138,498,140'Two-transistor floating-body dynamic memory cell'20138,258,035'Method to improve source/drain parasitics in vertical devices'20128,088,657'Integrated circuit using FinFETs and having a static random access memory (SRAM)'20128,076,215'Method of forming an electronic device using a separation technique'20118,043,888'Phase change memory cell with heater and method therefor'20117,998,822'Semiconductor fabrication process including silicide stringer removal processing'20117,910,482'Method of forming a finFET and structure'20117,829,447'Semiconductor structure pattern formation'20107,820,491'Light erasable memory and method therefor'20107,817,387'MIGFET circuit with ESD protection'20107,811,889'FinFET memory cell having a floating gate and method therefor'20107,803,670'Twisted dual-substrate orientation (DSO) substrates'20107,754,560'Integrated circuit using FinFETs and having a static random access memory (SRAM)'20107,749,884'Method of forming an electronic device using a separation-enhancing species'20107,737,018'Process of forming an electronic device including forming a gate electrode layer and forming a patterned masking layer'20107,727,829'Method of forming a semiconductor device having a removable sidewall spacer'20107,709,303'Process for forming an electronic device including a fin-type structure'20107,612,619'Phase detector device and method thereof'20097,611,936'Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method'20097,585,735'Asymmetric spacers and asymmetric source/drain extension layers'20097,573,114'Electronic device including a gated diode'20097,566,623'Electronic device including a semiconductor fin having a plurality of gate electrodes and a process for forming the electronic device'20097,521,720'Semiconductor optical devices having fin structures'20097,504,302'Process of forming a non-volatile memory cell including a capacitor structure'20097,494,832'Semiconductor optical devices and method for forming'20097,479,429'Split game memory cell method'20097,470,951'Hybrid-FET and its application as SRAM'20087,452,768'Multiple device types including an inverted-T channel transistor and method therefor'20087,446,006'Semiconductor fabrication process including silicide stringer removal processing'20087,446,001'Method for forming a semiconductor-on-insulator (SOI) body-contacted device with a portion of drain region removed'20087,439,791'Temperature compensation device and method thereof'20087,432,122'Electronic device and a process for forming the electronic device'20087,427,549'Method of separating a structure in a semiconductor device'20087,323,373'Method of forming a semiconductor device with decreased undercutting of semiconductor material'20087,301,741'Integrated circuit with multiple independent gate field effect transistor (MIGFET) rail clamp circuit'20077,282,426'Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof'20077,279,997'Voltage controlled oscillator with a multiple gate transistor and method therefor'20077,265,059'Multiple fin formation'20077,241,695'Semiconductor device having nano-pillars and method therefor'20077,238,601'Semiconductor device having conductive spacers in sidewall regions and method for forming'20077,215,268'Signal converters with multiple gate devices'20077,192,876'Transistor with independent gate structures'20077,112,455'Semiconductor optical devices and method for forming'20067,112,832'Transistor having multiple channels'20067,109,550'Semiconductor fabrication process with asymmetrical conductive spacers'20067,098,502'Transistor having three electrically isolated electrodes and method of formation'20067,018,876'Transistor with vertical dielectric structure'20067,013,447'Method for converting a planar transistor design to a vertical double gate transistor design'20066,969,656'Method and circuit for multiplying signals with a transistor having more than one independent gate structure'20056,967,143'Semiconductor fabrication process with asymmetrical conductive spacers'20056,951,783'Confined spacers for double gate transistor semiconductor fabrication process'20056,921,700'Method of forming a transistor having multiple channels'20056,903,967'Memory with charge storage locations and adjacent gate structures'20056,838,322'Method for forming a double-gated semiconductor device'20056,831,310'Integrated circuit having multiple memory types and method of formation'20046,753,216'Multiple gate transistor employing monocrystalline silicon walls'20046,686,245'Vertical MOSFET with asymmetric gate structure'20045,897,343'Method of making a power switching trench MOSFET having aligned source regions'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999Based in Chandler, AZ, US· patent location history
2004–2014Patents assigned to FREESCALE SEMICONDUCTOR INC (57)· patent assignee history
2004–2014Based in Austin, TX, US· patent location history
2010–2011Patents assigned to ASTROWATT INC (2)· patent assignee history
2011–2014Patents assigned to MATHEW LEO (8)· patent assignee history
2011–2013Patents assigned to JAWARANI DHARMESH (2)· patent assignee history
2012–2014Patents assigned to BURNETT JAMES D (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
FREESCALE SEMICONDUCTOR INC572004–2014
MATHEW LEOself82011–2014
ASTROWATT INC22010–2011
BURNETT JAMES D22012–2014
JAWARANI DHARMESH22011–2013
Locations
LocationPatentsSpan
Austin, Texas, US612004–2014
Chandler, AZ, US11999