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Inventor

Masatoshi Nishikawa

Inventor
Yokkaichi, JP

Overview

43→
Patents
1981–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 43 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary
H01LSemiconductor devices24%
H10BElectronic memory devices24%
H10DInorganic electric semiconductor devices23%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
G11CStatic stores5%
B26BHand-held cutting tools not otherwise provided for1%
B42CBookbinding1%
PatentTitleYear
11,094,715Three-dimensional memory device including different height memory stack structures and methods of making the same202111,081,185Non-volatile memory array driven from both sides for performance improvement202110,878,907Sub-block size reduction for 3D non-volatile memory202010,854,619Three-dimensional memory device containing bit line switches202010,839,918Boost converter in memory chip202010,797,062Bonded die assembly using a face-to-back oxide bonding and methods for making the same202010,756,106Three-dimensional memory device with locally modulated threshold voltages at drain select levels and methods of making the same202010,741,576Three-dimensional memory device containing drain-select-level air gap and methods of making the same202010,741,535Bonded assembly containing multiple memory dies sharing peripheral circuitry on a support die and methods for making the same202010,741,579Three-dimensional memory device including different height memory stack structures and methods of making the same202010,734,080Three-dimensional memory device containing bit line switches202010,720,444Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same202010,700,078Three-dimensional flat NAND memory device having curved memory elements and methods of making the same202010,700,090Three-dimensional flat NAND memory device having curved memory elements and methods of making the same202010,629,675Three-dimensional memory device containing capacitor pillars and methods of making the same202010,622,367Three-dimensional memory device including three-dimensional bit line discharge transistors and method of making the same202010,600,800Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same202010,580,787Three-dimensional memory device containing dummy antenna diodes202010,559,582Three-dimensional memory device containing source contact to bottom of vertical channels and method of making the same202010,515,897Three-dimensional memory device containing hydrogen diffusion blocking structures and method of making the same201910,516,025Three-dimensional NAND memory containing dual protrusion charge trapping regions and methods of manufacturing the same201910,475,804Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same201910,381,376Three-dimensional flat NAND memory device including concave word lines and method of making the same201910,354,980Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same201910,354,987Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same20199,941,297Vertical resistor in 3D memory device with two-tier stack20189,935,123Within array replacement openings for a three-dimensional memory device20189,935,124Split memory cells with unsplit select gates in a three-dimensional memory device20189,911,748'Epitaxial source region for uniform threshold voltage of vertical transistors in 3D memory devices'20189,859,422'Field effect transistor with elevated active regions and methods of manufacturing the same'20189,837,4313D semicircular vertical NAND string with recessed inactive semiconductor channel sections20179,799,670'Three dimensional NAND device containing dielectric pillars for a buried source line and method of making thereof'20179,691,781'Vertical resistor in 3D memory device with two-tier stack'20179,646,981'Passive devices for integration with three-dimensional memory devices'20179,616,698'Bookbinding apparatus'20179,620,512'Field effect transistor with a multilevel gate electrode for integration with a multilevel memory device'20179,589,981'Passive devices for integration with three-dimensional memory devices'20178,563,382'Semiconductor device'20138,409,958'Method of manufacturing semiconductor device'20138,329,570'Method of manufacturing semiconductor device'20128,222,706'Semiconductor device'20124,435,901'Method of manufacturing scissors and scissors'19844,250,620'Plastic scissors with metallic cutting inserts'1981

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1981–2017Patents assigned to NISHIKAWA MASATOSHI (7)· patent assignee history
1981–1984Based in Aichi, JP· patent location history
2012–2013Patents assigned to FUJITSU SEMICONDUCTOR LTD (4)· patent assignee history
2012Patents assigned to FUKUDA MASAHIRO (1)· patent assignee history
2012–2013Based in Yokohama, JP· patent location history
2017–2021Patents assigned to SANDISK TECHNOLOGIES LLC (36)· patent assignee history
2017–2018Patents assigned to SANDISK TECHNOLOGIES INC (8)· patent assignee history
2017–2020Based in Yokkaichi, JP· patent location history
2020Based in Nagoya, JP· patent location history
2021Based in Nagoya-shi, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SANDISK TECHNOLOGIES LLC362017–2021
SANDISK TECHNOLOGIES INC82017–2018
NISHIKAWA MASATOSHIself71981–2017
FUJITSU SEMICONDUCTOR LTD42012–2013
FUKUDA MASAHIRO12012
Locations
LocationPatentsSpan
Yokkaichi, JP192017–2020
Nagoya, JP132020
Yokohama, JP42012–2013
Nagoya-shi, JP22021
Aichi, JP21981–1984