Inventor
Randy J. Koval
Inventor
Boise, ID, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices23%
H10BElectronic memory devices23%
H10DInorganic electric semiconductor devices22%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
G11CStatic stores14%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
PatentTitleYear
11,088,168Semiconductor devices and methods of fabrication202111,037,633Methods and apparatuses including an asymmetric assist device202110,825,831Non-volatile memory with storage nodes having a radius of curvature202010,622,450Modified floating gate and dielectric layer geometry in 3D memory arrays202010,608,004Semiconductor devices and methods of fabrication202010,297,325Methods and apparatuses including an asymmetric assist device201910,128,262Vertical memory having varying storage cell design through the storage cell stack201810,038,002Semiconductor devices and methods of fabrication20189,953,842Methods of forming a portion of a memory array having a conductor having a variable concentration of germanium20189,875,801Methods and apparatuses including an asymmetric assist device20189,722,074'Local buried channel dielectric for vertical NAND performance enhancement and vertical scaling'20179,698,022'Self-aligned floating gate in a vertical memory structure'20179,666,449'Conductors having a variable concentration of germanium for governing removal rates of the conductor during control gate formation'20179,443,864'Self-aligned floating gate in a vertical memory structure'20169,196,625'Self-aligned floating gate in a vertical memory structure'20159,190,490'Local buried channel dielectric for vertical NAND performance enhancement and vertical scaling'20159,082,714'Use of etch process post wordline definition to improve data retention in a flash memory device'20158,878,279'Self-aligned floating gate in a vertical memory structure'2014Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2014–2020Patents assigned to INTEL CORP (10)· patent assignee history
2014–2021Based in Boise, ID, US· patent location history
2015–2017Patents assigned to KOVAL RANDY J (2)· patent assignee history
2015Patents assigned to GRAETTINGER THOMAS M (1)· patent assignee history
2015Patents assigned to HINEMAN MAX F (1)· patent assignee history
2017–2021Patents assigned to MICRON TECHNOLOGY INC (8)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 10 | 2014–2020 |
| MICRON TECHNOLOGY INC | 8 | 2017–2021 |
| KOVAL RANDY Jself | 2 | 2015–2017 |
| GRAETTINGER THOMAS M | 1 | 2015 |
| HINEMAN MAX F | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 18 | 2014–2021 |