Inventor

Christopher J. Penny

Inventor

Saratoga Springs, NY, US

Overview

2009–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 108 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices31%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%

H10DInorganic electric semiconductor devices6%

H10NElectric solid-state devices not otherwise provided for2%

G06FElectric digital data processing2%

H10KOrganic electric solid-state devices1%

G01NInvestigating or analysing materials by determining their chemical or physical properties1%

H01JElectric discharge tubes or discharge lamps1%

H04NPictorial communication, e.g. television1%

PatentTitleYear

11,113,533Smart display apparatus and control system2021 11,062,943Top via interconnects with wrap around liner2021 11,056,429Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device2021 11,018,007Self aligned pattern formation post spacer etchback in tight pitch configurations2021 11,005,646Blockchain stochastic timer transaction synchronization2021 11,004,790Method of manufacturing an interconnect without dielectric exclusion zones by thermal decomposition of a sacrificial filler material2021 10,978,393Hybrid dielectric scheme for varying liner thickness and manganese concentration2021 10,978,343Interconnect structure having fully aligned vias2021 10,971,030Remote physical training2021 10,964,588Selective ILD deposition for fully aligned via with airgap2021 10,957,583Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs2021 10,943,866Method and structure to construct cylindrical interconnects to reduce resistance2021 10,916,154Language learning and speech enhancement through natural language processing2021 10,833,149Capacitors2020 10,785,590Binaural audio calibration2020 10,784,156Self-aligned airgaps with conductive lines and vias2020 10,784,197Method and structure to construct cylindrical interconnects to reduce resistance2020 10,770,653Selective dielectric deposition to prevent gouging in MRAM2020 10,763,166Self-forming barrier for use in air gap formation2020 10,763,160Semiconductor device with selective insulator for improved capacitance2020 10,679,934Capacitance reduction in sea of lines BEOL metallization2020 10,658,154System and method for performing nano beam diffraction analysis2020 10,651,078Selective ILD deposition for fully aligned via with airgap2020 10,629,529Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device2020 10,629,478Dual-damascene formation with dielectric spacer and thin liner2020 10,629,428Metal insulator metal capacitor devices2020 10,606,231Computer-mediated reality including physical damping feedback2020 10,566,414BEOL capacitor through airgap metallization2020 10,566,231Interconnect formation with chamferless via, and related interconnect2020 10,546,774Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs2020 10,545,806Proximity correction in three-dimensional manufacturing2020 10,546,813BEOL vertical fuse formed over air gap2020 10,541,206Interconnect structure including air gaps enclosed between conductive lines and a permeable dielectric layer2020 10,529,569Self aligned pattern formation post spacer etchback in tight pitch configurations2020 10,529,662Method and structure to construct cylindrical interconnects to reduce resistance2020 10,528,817Smart display apparatus and control system2020 10,492,019Binaural audio calibration2019 10,475,878BEOL capacitor through airgap metallization2019 10,453,793BEOL vertical fuse formed over air gap2019 10,395,985Self aligned conductive lines with relaxed overlay2019 10,388,525Multi-angled deposition and masking for custom spacer trim and selected spacer removal2019 10,366,952Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device2019 10,366,940Air gap and air spacer pinch off2019 10,361,079Multi-angled deposition and masking for custom spacer trim and selected spacer removal2019 10,361,157Method of manufacturing self-aligned interconnects by deposition of a non-conformal air-gap forming layer having an undulated upper surface2019 10,361,117Selective ILD deposition for fully aligned via with airgap2019 10,347,825Selective deposition and nitridization of bottom electrode metal for MRAM applications2019 10,312,434Selective deposition and nitridization of bottom electrode metal for MRAM applications2019 10,283,586Capacitors2019 10,256,171Air gap and air spacer pinch off2019 10,256,191Hybrid dielectric scheme for varying liner thickness and manganese concentration2019 10,242,933Air gap and air spacer pinch off2019 10,229,967High-density MIM capacitors2019 10,229,851Self-forming barrier for use in air gap formation2019 10,177,076Air gap and air spacer pinch off2019 10,170,416Selective blocking boundary placement for circuit locations requiring electromigration short-length2019 10,170,540Capacitors2019 10,170,411Airgap protection layer for via alignment2019 10,121,661Self aligned pattern formation post spacer etchback in tight pitch configurations2018 10,109,579Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device2018 10,109,455System and method for performing nano beam diffraction analysis2018 10,083,905Skip-vias bypassing a metallization level at minimum pitch2018 10,083,864Self aligned conductive lines with relaxed overlay2018 10,083,908BEOL vertical fuse formed over air gap2018 10,056,290Self-aligned pattern formation for a semiconductor device2018 10,002,762Multi-angled deposition and masking for custom spacer trim and selected spacer removal2018 9,997,451Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device2018 9,997,454BEOL vertical fuse formed over air gap2018 9,991,156Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs2018 9,978,560System and method for performing nano beam diffraction analysis2018 9,972,533Aligning conductive vias with trenches2018 9,966,305Ion flow barrier structure for interconnect metallization2018 9,966,337Fully aligned via with integrated air gaps2018 9,960,117Air gap semiconductor structure with selective cap bilayer2018 9,934,970Self aligned pattern formation post spacer etchback in tight pitch configurations2018 9,929,088'Airgap protection layer for via alignment'2018 9,911,647'Self aligned conductive lines'2018 9,911,651'Skip-vias bypassing a metallization level at minimum pitch'2018 9,905,513'Selective blocking boundary placement for circuit locations requiring electromigration short-length'2018 9,899,256'Self-aligned airgaps with conductive lines and vias'2018 9,899,338'Structure and fabrication method for enhanced mechanical strength crack stop'2018 9,852,946Self aligned conductive lines2017 9,837,355Method for maximizing air gap in back end of the line interconnect through via landing modification2017 9,837,485High-density MIM capacitors2017 9,837,305Forming deep airgaps without flop over2017 9,824,982'Structure and fabrication method for enhanced mechanical strength crack stop'2017 9,793,213'Ion flow barrier structure for interconnect metallization'2017 9,793,193'Air gap and air spacer pinch off'2017 9,793,206'Heterogeneous metallization using solid diffusion removal of metal interconnects'2017 9,786,760'Air gap and air spacer pinch off'2017 9,786,554'Self aligned conductive lines'2017 9,779,944'Method and structure for cut material selection'2017 9,780,027'Hybrid airgap structure with oxide liner'2017 9,773,700'Aligning conductive vias with trenches'2017 9,711,455'Method of forming an air gap semiconductor structure with selective cap bilayer'2017 9,685,366'Forming chamferless vias using thermally decomposable porefiller'2017 9,666,528'BEOL vertical fuse formed over air gap'2017 9,666,529'Method and structure to reduce the electric field in semiconductor wiring interconnects'2017 9,607,943'Capacitors'2017 9,607,886'Self aligned conductive lines with relaxed overlay'2017 9,553,019'Airgap protection layer for via alignment'2017 9,449,871'Hybrid airgap structure with oxide liner'2016 9,379,057'Method and structure to reduce the electric field in semiconductor wiring interconnects'2016 9,349,687'Advanced manganese/manganese nitride cap/etch mask for air gap formation scheme in nanocopper low-K interconnect'2016 9,305,836'Air gap semiconductor structure with selective cap bilayer'2016 9,105,641'Profile control in interconnect structures'2015 8,835,305'Method of fabricating a profile control in interconnect structures'2014 7,544,609'Method for integrating liner formation in back end of line processing'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009–2021Patents assigned to IBM (100)· patent assignee history

2009–2017Based in Poughkeepsie, NY, US· patent location history

2014–2016Patents assigned to PENNY CHRISTOPHER J (2)· patent assignee history

2014Patents assigned to CHEN SHYNG-TSONG (1)· patent assignee history

2016–2021Based in Saratoga Springs, NY, US· patent location history

2018–2020Based in Albany, NY, US· patent location history

2020–2021Patents assigned to TESSERA INC (6)· patent assignee history

2020Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	100	2009–2021
TESSERA INC	6	2020–2021
GLOBALFOUNDRIES INC	2	2020
PENNY CHRISTOPHER Jself	2	2014–2016
CHEN SHYNG-TSONG	1	2014

Locations

Location	Patents	Span
Saratoga Springs, New York, US	99	2016–2021
Poughkeepsie, New York, US	6	2009–2017
Albany, New York, US	3	2018–2020