Inventor
Yvon Savaria
Inventor
Montreal, CA
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices18%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H03KPulse technique12%
H01CResistors9%
H04LTransmission of digital information, e.g. telegraphic communication9%
G06FElectric digital data processing6%
A61NElectrotherapy3%
G01RMeasuring electric variables3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
PatentTitleYear
9,076,809'Tunable semiconductor component provided with a current barrier'20158,759,191'Tunable semiconductor component provided with a current barrier'20147,693,490'Multi-equalization method and apparatus'20107,609,778'Methods, apparatus, and systems for reducing interference on nearby conductors'20097,564,078'Tunable semiconductor component provided with a current barrier'20097,546,570'Communications bus for a parallel processing system'20097,217,986'Method for modifying the impedance of semiconductor devices using a focused heating source'20077,027,874'Body electronic implant and artificial vision system thereof'20066,928,606'Fault tolerant scan chain for a parallel processing system'20056,897,497'Methods, apparatus, and systems for reducing interference on nearby conductors'20056,890,802'Method for modifying the impedance of semiconductor devices using a focused heating source'20056,858,356'Method of generating large scale signal paths in a parallel processing system'20056,703,868'Methods, apparatus, and systems for reducing interference on nearby conductors'20046,329,272'Method and apparatus for iteratively, selectively tuning the impedance of integrated semiconductor devices using a focussed heating source'20016,100,716'Voltage excursion detection apparatus'20005,276,893'Parallel microprocessor architecture'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2009Patents assigned to SAVARIA YVON (2)· patent assignee history
1994Based in Quebec, CA· patent location history
2000–2015Based in Montreal, CA· patent location history
2001–2007Patents assigned to TECHNOLOGIES LTRIM INC (2)· patent assignee history
2004–2009Patents assigned to HYPERCHIP INC (4)· patent assignee history
2005–2009Based in Montréal, CA· patent location history
2009–2015Patents assigned to CADEKA MICROCIRCUITS LLC (3)· patent assignee history
2009Patents assigned to BLAQUIERE YVES (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HYPERCHIP INC | 4 | 2004–2009 |
| CADEKA MICROCIRCUITS LLC | 3 | 2009–2015 |
| SAVARIA YVONself | 2 | 1994–2009 |
| TECHNOLOGIES LTRIM INC | 2 | 2001–2007 |
| BLAQUIERE YVES | 1 | 2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| Montreal, CA | 11 | 2000–2015 |
| Montréal, CA | 4 | 2005–2009 |
| Quebec, CA | 1 | 1994 |