Inventor
Siegfried Schwarzl
Inventor
Neubiberg, DE
Overview
Patents· 40 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
B82Yprimary
B82YSpecific uses or applications of nanostructures17%
G11CStatic stores17%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices13%
H10BElectronic memory devices13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
H10NElectric solid-state devices not otherwise provided for5%
G21KHandling of particles or ionising radiation not otherwise provided for4%
Y10TTechnical subjects covered by former us classification4%
H01FMagnets3%
H10DInorganic electric semiconductor devices3%
PatentTitleYear
8,501,373'Passivation of multi-layer mirror for extreme ultraviolet lithography'20138,076,055'Passivation of multi-layer mirror for extreme ultraviolet lithography'20117,859,648'Passivation of multi-layer mirror for extreme ultraviolet lithography'20107,626,682'Reticle stages for lithography systems and lithography methods'20097,417,736'Method for determining a radiation power and an exposure apparatus'20087,407,729'EUV magnetic contrast lithography mask and manufacture thereof'20087,341,875'Semiconductor memory device with a capacitor formed therein and a method for forming the same'20087,332,444'Method for smoothing areas in structures by utilizing the surface tension'20087,323,821'Device for generating and/or influencing electromagnetic radiation from a plasma'20087,316,933'Method for producing an annular microstructure element'2008RE039799'Memory cell array and method for manufacturing it'20077,259,441'Hollow structure in an integrated circuit and method for producing such a hollow structure in an integrated circuit'20077,078,134'Photolithographic mask having a structure region covered by a thin protective coating of only a few atomic layers and methods for the fabrication of the mask including ALCVD to form the thin protective coating'20067,064,439'Integrated electrical circuit and method for fabricating it'20067,029,808'Photosensitive coating material for a substrate and process for exposing the coated substrate'20067,023,063'Arrangement of microstructures'20066,943,393'Memory cell arrangement and method of fabricating it'20056,930,052'Method for producing an integrated circuit having at least one metalicized surface'20056,925,002'Semiconductor memory having mutually crossing word and bit lines, at which magnetoresistive memory cells are arranged'20056,872,495'Method for fabricating a lithographic reflection mask in particular for the patterning of a semiconductor wafer, and a reflection mask'20056,849,365'Reflection mask for EUV-lithography and method for fabricating the reflection mask'20056,825,098'Method for fabricating microstructures and arrangement of microstructures'20046,717,843'Polyvalent, magnetoresistive write/read memory and method for writing and reading a memory of this type'20046,686,643'Substrate with at least two metal structures deposited thereon, and method for fabricating the same'20046,630,703'Magnetoresistive memory cell configuration and method for its production'20036,605,837'Memory cell configuration and production method'20036,579,729'Memory cell configuration and method for fabricating it'20036,577,526'Magnetoresistive element and the use thereof as storage element in a storage cell array'20036,574,138'Memory cell configuration and method for operating the configuration'20036,510,078'Memory cell array and method for manufacturing it'20036,495,873'Magnetoresistive element and use thereof as a memory element in a memory cell configuration'20026,462,980'MRAM memory with drive logic arrangement'20026,458,603'Method of fabricating a micro-technical structure, and micro-technical component'20026,424,562'Read/write architecture for MRAM'20026,379,978'Memory cell configuration in which an electrical resistance of a memory element represents an information item and can be influenced by a magnetic field, and method for fabricating it'20026,351,408'Memory cell configuration'20025,626,279'Method for fastening a first substrate on a second substrate and employment of said method for manufacturing a three-dimensional circuit arrangement'19975,529,950'Method for manufacturing a cubically integrated circuit arrangement'19965,262,002'Method for manufacturing a trench structure in a substrate'19934,581,319'Method for the manufacture of bipolar transistor structures with self-adjusting emitter and base regions for extreme high frequency circuits'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986–2003Patents assigned to SIEMENS AG (5)· patent assignee history
1986Based in Ottobrunn, DE· patent location history
1993–2013Based in Neubiberg, DE· patent location history
2002–2013Patents assigned to INFINEON TECHNOLOGIES AG (34)· patent assignee history
2008Patents assigned to QIMONDA AG (1)· patent assignee history
2009Based in Bavaria, DE· patent location history
2011–2013Patents assigned to SCHWARZL SIEGFRIED (2)· patent assignee history
2011–2013Patents assigned to WURM STEFAN (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INFINEON TECHNOLOGIES AG | 34 | 2002–2013 |
| SIEMENS AG | 5 | 1986–2003 |
| SCHWARZL SIEGFRIEDself | 2 | 2011–2013 |
| WURM STEFAN | 2 | 2011–2013 |
| QIMONDA AG | 1 | 2008 |
Locations
| Location | Patents | Span |
|---|---|---|
| Neubiberg, DE | 38 | 1993–2013 |
| Bavaria, DE | 1 | 2009 |
| Ottobrunn, DE | 1 | 1986 |