Inventor
Laertis Economikos
Inventor
Wappingers Falls, NY, US
Overview
Patents· 105 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10DInorganic electric semiconductor devices17%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H01LSemiconductor devices16%
H05KPrinted circuits6%
Y10TTechnical subjects covered by former us classification5%
H10BElectronic memory devices4%
B23KSoldering or unsoldering3%
B24BMachines, devices, or processes for grinding or polishing3%
B26DCutting1%
PatentTitleYear
10,998,422Methods, apparatus and system for a self-aligned gate cut on a semiconductor device202110,937,786Gate cut structures202110,923,469Vertical resistor adjacent inactive gate over trench isolation202110,879,073Insulating gate separation structure for transistor devices202010,790,363IC structure with metal cap on cobalt layer and methods of forming same202010,741,656Wraparound contact surrounding source/drain regions of integrated circuit structures and method of forming same202010,741,451FinFET having insulating layers between gate and source/drain contacts202010,727,136Integrated gate contact and cross-coupling contact formation202010,707,206Gate cut isolation formed as layer against sidewall of dummy gate mandrel202010,699,957Late gate cut using selective dielectric deposition202010,586,860Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process202010,580,685Integrated single diffusion break202010,573,753Oxide spacer in a contact over active gate finFET and method of production thereof202010,566,201Gate cut method after source/drain metallization202010,553,698Methods, apparatus and system for a self-aligned gate cut on a semiconductor device202010,553,486Field effect transistors with self-aligned metal plugs and methods202010,546,853Metal resistors integrated into poly-open-chemical-mechanical-polishing (POC) module and method of production thereof202010,535,771Method for forming replacement air gap202010,522,538Using source/drain contact cap during gate cut201910,522,410Performing concurrent diffusion break, gate and source/drain contact cut etch processes201910,510,613Contact structures201910,510,749Resistor within single diffusion break, and related method201910,504,798Gate cut in replacement metal gate process201910,475,791Transistor fins with different thickness gate dielectric201910,418,285Fin field-effect transistor (FinFET) and method of production thereof201910,388,652Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same201910,388,747Gate contact structure positioned above an active region with air gaps positioned adjacent the gate structure201910,373,877Methods of forming source/drain contact structures on integrated circuit products201910,373,875Contacts formed with self-aligned cuts201910,373,873Gate cut in replacement metal gate process201910,276,391Self-aligned gate caps with an inverted profile201910,236,213Gate cut structure with liner spacer and related method201910,199,271Self-aligned metal wire on contact structure and method for forming same201910,177,041Fin-type field effect transistors (FINFETS) with replacement metal gates and methods201910,157,796Forming of marking trenches in structure for multiple patterning lithography201810,109,505Dual medium filter for ion and particle filtering during semiconductor processing201810,090,402Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates201810,056,469Gate cut integration and related device20189,966,272Methods for nitride planarization using dielectric20189,676,075'Methods and structures for achieving target resistance post CMP using in-situ resistance measurements'20179,607,864'Dual medium filter for ion and particle filtering during semiconductor processing'20179,058,976'Cleaning composition and process for cleaning semiconductor devices and/or tooling during manufacturing thereof'20158,858,300'Applying different pressures through sub-pad to fixed abrasive CMP pad'20148,822,994'Method of repairing probe pads'20148,792,080'Method and system to predict lithography focus error using simulated or measured topography'20148,748,252'Replacement metal gate transistors using bi-layer hardmask'20148,324,622'Method of repairing probe pads'20128,143,166'Polishing method with inert gas injection'20128,117,568'Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design'20127,993,498'Apparatus and method of electrolytic removal of metals from a wafer surface'20117,473,159'Detection of diamond contamination in polishing pad and reconditioning system therefor'20097,470,985'Solder connector structure and method'20087,354,333'Detection of diamond contamination in polishing pad'20087,214,623'Planarization system and method using a carbonate containing fluid'20077,091,103'TEOS assisted oxide CMP process'20067,040,966'Carbonation of pH controlled KOH solution for improved polishing of oxide films on semiconductor wafers'20066,869,860'Filling high aspect ratio isolation structures with polysilazane based material'20056,794,242'Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts'20046,776,885'Integrated plating and planarization apparatus having a variable-diameter counterelectrode'20046,773,570'Integrated plating and planarization process and apparatus therefor'20046,656,817'Method of filling isolation trenches in a substrate'20036,596,580'Recess Pt structure for high k stacked capacitor in DRAM and FRAM, and the method to form this structure'20036,569,769'Slurry-less chemical-mechanical polishing'20036,485,355'Method to increase removal rate of oxide using fixed-abrasive'20026,448,169'Apparatus and method for use in manufacturing semiconductor devices'20026,444,919'Thin film wiring scheme utilizing inter-chip site surface wiring'20026,429,149'Low temperature LPCVD PSG/BPSG process'20026,403,412'Method for in-situ formation of bottle shaped trench by gas phase etching'20026,368,969'Chemical-mechanical polishing methods'20026,365,328'Semiconductor structure and manufacturing method'20026,359,300'High aspect ratio deep trench capacitor having void-free fill'20026,358,850'Slurry-less chemical-mechanical polishing of oxide materials'20026,350,692'Increased polish removal rate of dielectric layers using fixed abrasive pads'20026,335,261'Directional CVD process with optimized etchback'20026,319,794'Structure and method for producing low leakage isolation devices'20016,294,470'Slurry-less chemical-mechanical polishing'20016,276,246'Method for punching slug from workpiece'20016,218,236'Method of forming a buried bitline in a vertical DRAM device'20016,208,008'Integrated circuits having reduced stress in metallization'20016,198,167'Semiconductor structure exhibiting reduced contact resistance and method for fabrication'20016,180,480'Germanium or silicon-germanium deep trench fill by melt-flow process'20016,177,696'Integration scheme enhancing deep trench capacitance in semiconductor integrated circuit devices'20016,149,048'Apparatus and method for use in manufacturing semiconductor devices'20006,136,664'Filling of high aspect ratio trench isolation'20006,099,935'Apparatus for providing solder interconnections to semiconductor and electronic packaging devices'20006,057,216'Low temperature diffusion process for dopant concentration enhancement'20006,037,193'Hermetic sealing of a substrate of high thermal conductivity using an interposer of low thermal conductivity'20006,030,881'High throughput chemical vapor deposition process capable of filling high aspect ratio structures'20006,003,418'Punched slug removal system'19995,945,735'Hermetic sealing of a substrate of high thermal conductivity using an interposer of low thermal conductivity'19995,939,335'Method for reducing stress in the metallization of an integrated circuit'19995,907,985'Punch apparatus with improved slug removal efficiency'19995,904,868'Mounting and/or removing of components using optical fiber tools'19995,742,021'High thermal conductivity substrate and the method of brazing a cap thereto'19985,536,605'Method of repairing apertured laser metal mask'19965,534,371'Repaired apertured laser metal mask'19965,491,319'Laser ablation apparatus and method'19965,481,138'Structure and a method for repairing electrical lines'19965,478,009'Selective removal of a single solder ball from an array of solder balls'19955,425,493'Selective addition of a solder ball to an array of solder balls'19955,384,953'Structure and a method for repairing electrical lines'19955,321,886'Applying conductive lines to integrated circuits'19945,310,967'Applying conductive lines to integrated circuits'19945,289,632'Applying conductive lines to integrated circuits'19945,235,154'Laser removal of metal interconnects'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–2018Patents assigned to IBM (64)· patent assignee history
1993–2021Based in Wappingers Falls, NY, US· patent location history
2002–2004Patents assigned to INFINEON TECHNOLOGIES AG (4)· patent assignee history
2012–2017Patents assigned to ECONOMIKOS LAERTIS (7)· patent assignee history
2012–2018Patents assigned to ST MICROELECTRONICS INC (4)· patent assignee history
2012Based in Highland Falls, NY, US· patent location history
2014Based in Hopewell Junction, NY, US· patent location history
2017–2021Patents assigned to GLOBALFOUNDRIES INC (38)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 64 | 1993–2018 |
| GLOBALFOUNDRIES INC | 38 | 2017–2021 |
| ECONOMIKOS LAERTISself | 7 | 2012–2017 |
| INFINEON TECHNOLOGIES AG | 4 | 2002–2004 |
| ST MICROELECTRONICS INC | 4 | 2012–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Wappingers Falls, New York, US | 103 | 1993–2021 |
| Hopewell Junction, New York, US | 1 | 2014 |
| Highland Falls, New York, US | 1 | 2012 |