Inventor
Mohammad Abdallah
Inventor
El Dorado Hills, CA, US
Overview
Patents· 145 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing84%
H03MCoding3%
H04LTransmission of digital information, e.g. telegraphic communication3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
G06TImage data processing or generation, in general2%
LOC151%
B60TVehicle brake control systems or parts thereof1%
G11CStatic stores1%
PatentTitleYear
10,810,014Method and apparatus for guest return address stack emulation supporting speculation202010,740,126Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation202010,713,047Fast unaligned memory access202010,592,300Method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization202010,585,804Systems and methods for non-blocking implementation of cache flush instructions202010,585,670Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer202010,564,975Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines202010,521,239Microprocessor accelerated code optimizer201910,514,926Method and apparatus to allow early dependency resolution and data forwarding in a microprocessor201910,503,514Method for implementing a reduced size register view data structure in a microprocessor201910,467,010Method and apparatus for nearest potential store tagging201910,417,000Method for a delayed branch implementation by using a front end track table201910,394,563Hardware accelerated conversion system using pattern matching201910,372,454Allocation of a segmented interconnect to support the execution of instruction sequences by a plurality of engines201910,360,031Fast unaligned memory access201910,353,680System converter that implements a run ahead run time guest instruction conversion/decoding process and a prefetching process where guest code is pre-fetched from the target of guest branches in an instruction sequence201910,346,302Systems and methods for maintaining the coherency of a store coalescing cache and a load cache201910,310,987Systems and methods for accessing a unified translation lookaside buffer201910,303,484Method for implementing a line speed interconnect structure201910,289,419Method and apparatus for sorting elements in hardware structures201910,289,605Apparatus and method for processing an instruction matrix specifying parallel and dependent operations201910,282,170Method for a stage optimized high speed adder201910,275,255Method for dependency broadcasting through a source organized source view data structure201910,255,076Method for performing dual dispatch of blocks and half blocks201910,255,187Systems and methods for implementing weak stream software data and instruction prefetching using a hardware data prefetcher201910,248,570Methods, systems and apparatus for predicting the way of a set associative cache201910,241,795Guest to native block address mappings and management of native code storage201910,228,950Method and apparatus for guest return address stack emulation supporting speculation201910,228,949Single cycle multi-branch prediction including shadow cache for early far branch prediction201910,210,101Systems and methods for flushing a cache with modified data201910,198,266Method for populating register view data structure by using register template snapshots201910,191,746Accelerated code optimizer for a multiengine microprocessor201910,185,567Multilevel conversion table cache for translating guest instructions to native instructions201910,169,045Method for dependency broadcasting through a source organized source view data structure201910,146,576Method for executing multithreaded instructions grouped into blocks201810,146,548Method for populating a source view data structure by using register template snapshots201810,140,138Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation201810,083,041Instruction sequence buffer to enhance branch prediction efficiency201810,048,964Disambiguation-free out of order load store queue201810,042,643Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor201810,031,784Interconnect system to support the execution of instruction sequences by a plurality of partitionable engines201810,019,263Reordered speculative instruction sequences with a disambiguation-free out of order load store queue201810,013,254Systems and methods for load cancelling in a processor that is connected to an external interconnect fabric20189,990,198Instruction definition to implement load store reordering and optimization20189,990,200Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines20189,965,281Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer20189,965,277Virtual load store queue having a dynamic dispatch window with a unified structure20189,946,538Method and apparatus for providing hardware support for self-modifying code20189,940,134Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines20189,934,072Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines20189,934,042Method for dependency broadcasting through a block organized source view data structure20189,928,179'Cache replacement policy'20189,928,121'Method and system for implementing recovery from speculative forwarding miss-predictions/errors resulting from load store reordering and optimization'20189,921,845'Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines'20189,921,842'Guest instruction block with near branching and far branching sequence construction to native instruction block'20189,921,850'Instruction sequence buffer to enhance branch prediction efficiency'20189,904,552'Virtual load store queue having a dynamic dispatch window with a distributed structure'20189,904,625'Methods, systems and apparatus for predicting the way of a set associative cache'20189,898,412'Methods, systems and apparatus for predicting the way of a set associative cache'20189,891,915'Method and apparatus to increase the speed of the load access and data return speed path using early lower address bits'20189,891,924'Method for implementing a reduced size register view data structure in a microprocessor'20189,886,416'Apparatus and method for processing an instruction matrix specifying parallel and dependent operations'20189,886,279'Method for populating and instruction view data structure by using register template snapshots'20189,858,080'Method for implementing a reduced size register view data structure in a microprocessor'20189,858,206'Systems and methods for flushing a cache with modified data'20189,842,056'Systems and methods for non-blocking implementation of cache flush instructions'20179,842,005'Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines'20179,823,930'Method for emulating a guest centralized flag architecture by using a native distributed flag architecture'20179,823,939'System for an instruction set agnostic runtime architecture'20179,817,666'Method for a delayed branch implementation by using a front end track table'20179,811,342'Method for performing dual dispatch of blocks and half blocks'20179,811,377'Method for executing multithreaded instructions grouped into blocks'20179,767,038'Systems and methods for accessing a unified translation lookaside buffer'20179,766,893'Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines'20179,753,734'Method and apparatus for sorting elements in hardware structures'20179,753,856'Variable caching structure for managing physical storage'20179,753,691'Method for a stage optimized high speed adder'20179,740,612'Systems and methods for maintaining the coherency of a store coalescing cache and a load cache'20179,740,499'Method for implementing a line speed interconnect structure'20179,733,909'System converter that implements a reordering process through JIT (just in time) optimization that ensures loads do not dispatch ahead of other loads that are to the same address'20179,733,942'Mapping of guest instruction block assembled according to branch prediction to translated native conversion block'20179,733,944'Instruction sequence buffer to store branches having reliably predictable instruction sequences'20179,720,839'Systems and methods for supporting a plurality of load and store accesses of a cache'20179,720,831'Systems and methods for maintaining the coherency of a store coalescing cache and a load cache'20179,710,399'Systems and methods for flushing a cache with modified data'20179,710,387'Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor'20179,697,131'Variable caching structure for managing physical storage'20179,678,755'Instruction sequence buffer to enhance branch prediction efficiency'20179,678,882'Systems and methods for non-blocking implementation of cache flush instructions'20179,639,364'Guest to native block address mappings and management of native code storage'20179,575,762'Method for populating register view data structure by using register template snapshots'20179,569,216'Method for populating a source view data structure by using register template snapshots'20179,542,187'Guest instruction block with near branching and far branching sequence construction to native instruction block'20179,501,280'Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer'20169,454,491'Systems and methods for accessing a unified translation lookaside buffer'20169,442,772'Global and local interconnect structure comprising routing matrix to support the execution of instruction sequences by a plurality of engines'20169,436,476'Method and apparatus for sorting elements in hardware structures'20169,430,410'Systems and methods for supporting a plurality of load accesses of a cache in a single cycle'20169,424,046'Systems and methods for load canceling in a processor that is connected to an external interconnect fabric'20169,348,754'Systems and methods for implementing weak stream software data and instruction prefetching using a hardware data prefetcher'20169,274,793'Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines'20169,229,873'Systems and methods for supporting a plurality of load and store accesses of a cache'20169,207,960'Multilevel conversion table cache for translating guest instructions to native instructions'20159,053,292'Processor executing super instruction matrix with register file configurable for single or multiple threads operations'20158,930,674'Systems and methods for accessing a unified translation lookaside buffer'20158,732,226'Integer rounding operation'20148,677,105'Parallel processing of a sequential program using hardware generated threads and their instruction groups executing on plural execution units and accessing register file segments using dependency inheritance vectors across multiple engines'20148,342,076'Brake actuator and method of forming the same'20138,327,115'Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode'20127,761,694'Execution unit for performing shuffle and other operations'20107,516,307'Processor for computing a packed sum of absolute differences and packed multiply-add'20097,480,360'Regulating a timing between a strobe signal and a data signal'20097,467,286'Executing partial-width packed data instructions'20087,430,656'System and method of converting data formats and communicating between execution units'20087,216,138'Method and apparatus for floating point operations and format conversion operations'20077,133,040'System and method for performing an insert-extract instruction'20066,970,994'Executing partial-width packed data instructions'20056,918,032'Hardware predication for conditional instruction path branching'20056,754,812'Hardware predication for conditional instruction path branching'20046,718,440'Memory access latency hiding with hint buffer'20046,701,414'System and method for prefetching data into a cache based on miss distance'20046,584,549'System and method for prefetching data into a cache based on miss distance'20036,502,115'Conversion between packed floating point data and packed 32-bit integer data in different architectural registers'20026,498,605'Pixel span depth buffer'20026,480,868'Conversion from packed floating point data to packed 8-bit integer data in different architectural registers'20026,426,746'Optimization for 3-D graphic transformation using SIMD computations'20026,377,970'Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitry'20026,307,553'System and method for performing a MOVHPS-MOVLPS instruction'20016,292,815'Data conversion between floating point packed format and integer scalar format'20016,282,554'Method and apparatus for floating point operations and format conversion operations'20016,269,386'3X adder'20016,266,769'Conversion between packed floating point data and packed 32-bit integer data in different architectural registers'20016,263,426'Conversion from packed floating point data to packed 8-bit integer data in different architectural registers'20016,247,116'Conversion from packed floating point data to packed 16-bit integer data in different architectural registers'20016,243,803'Method and apparatus for computing a packed absolute differences with plurality of sign bits using SIMD add circuitry'20016,233,671'Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions'20016,192,467'Executing partial-width packed data instructions'2001D0435050'Reciprocating compressor'20006,122,725'Executing partial-width packed data instructions'20006,115,812'Method and apparatus for efficient vertical SIMD computations'20006,085,312'Method and apparatus for handling imprecise exceptions'20006,041,404'Dual function system and method for shuffling packed data elements'20006,035,318'Booth multiplier for handling variable width operands'2000D0419162'Reciprocating compressor'20005,469,376'Digital circuit for the evaluation of mathematical expressions'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2020Patents assigned to INTEL CORP (123)· patent assignee history
2000–2020Based in Folsom, CA, US· patent location history
2000–2013Based in Charlotte, NC, US· patent location history
2002Based in Folson, CA, US· patent location history
2012–2017Patents assigned to SOFT MACHINES INC (17)· patent assignee history
2012–2014Patents assigned to ABDALLAH MOHAMMAD A (2)· patent assignee history
2013–2019Patents assigned to ABDALLAH MOHAMMAD (25)· patent assignee history
2014–2019Based in San Jose, CA, US· patent location history
2015–2018Patents assigned to AVUDAIYAPPAN KARTHIKEYAN (7)· patent assignee history
2017–2020Based in El Dorado Hills, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 123 | 2000–2020 |
| ABDALLAH MOHAMMADself | 25 | 2013–2019 |
| SOFT MACHINES INC | 17 | 2012–2017 |
| AVUDAIYAPPAN KARTHIKEYAN | 7 | 2015–2018 |
| ABDALLAH MOHAMMAD Aself | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| El Dorado Hills, California, US | 72 | 2017–2020 |
| Folsom, California, US | 41 | 2000–2020 |
| San Jose, California, US | 27 | 2014–2019 |
| Charlotte, NC, US | 3 | 2000–2013 |
| Folson, California, US | 1 | 2002 |