Inventor
Brian K. Kirkpatrick
Inventor
Allen, TX, US
Overview
Patents· 44 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices36%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1036%
H01LSemiconductor devices14%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
B24BMachines, devices, or processes for grinding or polishing1%
C23CCoating metallic material1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
PatentTitleYear
10,483,261Integrated circuit having chemically modified spacer surface20199,881,795'Method of fabricating semiconductors'20189,768,078'Inner L-spacer for replacement gate flow'20179,721,847'High-k / metal gate CMOS transistors with TiN gates'20179,620,423'Integrated circuit having chemically modified spacer surface'20179,496,359'Integrated circuit having chemically modified spacer surface'20169,490,143'Method of fabricating semiconductors'20169,362,375'Inner L-spacer for replacement gate flow'20169,224,657'Hard mask for source/drain epitaxy control'20159,178,037'Inner L-spacer for replacement gate flow'20159,087,917'Inner L-spacer for replacement gate flow'20159,070,785'High-k / metal gate CMOS transistors with TiN gates'20158,748,996'Semiconductor device including SiON gate dielectric with portions having different nitrogen concentrations'20148,748,992'MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls'20148,618,661'Die having coefficient of thermal expansion graded layer'20138,450,221'Method of forming MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls'20138,441,078'Semiconductor device including SiON gate dielectric with portions having different nitrogen concentrations'20138,372,703'Gate dielectric first replacement gate processes and integrated circuits therefrom'20138,252,609'Curvature reduction for semiconductor wafers'20128,216,945'Wafer planarity control between pattern levels'20128,058,161'Recessed STI for wide transistors'20118,043,921'Nitride removal while protecting semiconductor surfaces for forming shallow junctions'20117,998,865'Systems and methods for removing wafer edge residue and debris using a residue remover mechanism'20117,968,443'Cross-contamination control for processing of circuits comprising MOS devices that include metal comprising high-K dielectrics'20117,943,456'Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom'20117,927,993'Cross-contamination control for semiconductor process flows having metal comprising gate electrodes'20117,838,356'Gate dielectric first replacement gate processes and integrated circuits therefrom'20107,785,957'Post metal gate VT adjust etch clean'20107,732,284'Post high-k dielectric/metal gate clean'20107,504,339'Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits'20097,402,524'Post high voltage gate oxide pattern high-vacuum outgas surface treatment'20087,384,869'Protection of silicon from phosphoric acid using thick chemical oxide'20087,339,240'Dual-gate integrated circuit semiconductor device'20087,186,651'Chemical mechanical polishing method and apparatus'20077,049,242'Post high voltage gate dielectric pattern plasma surface treatment'20067,018,925'Post high voltage gate oxide pattern high-vacuum outgas surface treatment'20066,921,721'Post plasma clean process for a hardmask'20056,917,093'Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits'20056,869,862'Method for improving a physical property defect value of a gate dielectric'20056,861,348'Pre-pattern surface modification of low-k dielectrics'20056,831,008'Nickel silicidesilicon nitride adhesion through surface passivation'20046,797,644'Method to reduce charge interface traps and channel hot carrier degradation'20046,720,247'Pre-pattern surface modification for low-k dielectrics using A H2 plasma'20046,287,983'Selective nitride etching with silicate ion pre-loading'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2019Patents assigned to TEXAS INSTRUMENTS INC (44)· patent assignee history
2001–2019Based in Allen, TX, US· patent location history
2011–2016Patents assigned to KIRKPATRICK BRIAN K (7)· patent assignee history
2012–2016Patents assigned to JAIN AMITABH (3)· patent assignee history
2012Patents assigned to PRINS STEVEN L (2)· patent assignee history
2013Patents assigned to CHAMBERS JAMES JOSEPH (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 44 | 2001–2019 |
| KIRKPATRICK BRIAN Kself | 7 | 2011–2016 |
| JAIN AMITABH | 3 | 2012–2016 |
| CHAMBERS JAMES JOSEPH | 2 | 2013 |
| PRINS STEVEN L | 2 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Allen, Texas, US | 44 | 2001–2019 |