Inventor
Michael Wise
Inventor
Lagrangeville, NY, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices20%
H04LTransmission of digital information, e.g. telegraphic communication18%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10BElectronic memory devices15%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
B24BMachines, devices, or processes for grinding or polishing5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
B62JCycle saddles or seats3%
Y10TTechnical subjects covered by former us classification3%
PatentTitleYear
9,674,254'System and method for using a streaming protocol'20179,184,916'System and method for using a streaming protocol'20158,634,552'System and method for using a streaming protocol'20148,284,931'System and method for using a streaming protocol'20127,734,042'System and method for using a streaming protocol'20107,698,415'Networked port-inventory system and method'20107,602,908'System and method for using a streaming protocol'20097,319,270'Multi-layer electrode and method of forming the same'20087,281,750'Self-adjusting motorcycle windshield'20077,270,884'Adhesion layer for Pt on SiO2'20077,091,103'TEOS assisted oxide CMP process'20066,821,865'Deep isolation trenches'20046,794,705'Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials'20046,696,759'Semiconductor device with diamond-like carbon layer as a polish-stop layer'20046,596,580'Recess Pt structure for high k stacked capacitor in DRAM and FRAM, and the method to form this structure'20036,437,401'Structure and method for improved isolation in trench storage cells'20026,420,216'Fuse processing using dielectric planarization pillars'20026,379,222'Methods and apparatus for chemical mechanical planarization (CMP) of a semiconductor wafer'20026,348,395'Diamond as a polish-stop layer for chemical-mechanical planarization in a damascene process flow'20026,020,262'Methods and apparatus for chemical mechanical planarization (CMP) of a semiconductor wafer'20005,915,175'Mitigation of CMP-induced BPSG surface damage by an integrated anneal and silicon dioxide deposition'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2002Patents assigned to SIEMENS AG (3)· patent assignee history
1999–2002Based in Poughkeepsie, NY, US· patent location history
2000–2007Patents assigned to IBM (8)· patent assignee history
2002–2008Patents assigned to INFINEON TECHNOLOGIES AG (5)· patent assignee history
2002–2006Patents assigned to INFINEON TECHNOLOGIES CORP (3)· patent assignee history
2002–2008Based in Lagrangeville, NY, US· patent location history
2007Based in Larangeville, NY, US· patent location history
2009–2017Based in Washington, DC, US· patent location history
2010–2017Patents assigned to AOL INC (4)· patent assignee history
2010Based in Orrick, MO, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 8 | 2000–2007 |
| INFINEON TECHNOLOGIES AG | 5 | 2002–2008 |
| AOL INC | 4 | 2010–2017 |
| INFINEON TECHNOLOGIES CORP | 3 | 2002–2006 |
| SIEMENS AG | 3 | 1999–2002 |
Locations
| Location | Patents | Span |
|---|---|---|
| Lagrangeville, New York, US | 10 | 2002–2008 |
| Washington, DC, US | 6 | 2009–2017 |
| Poughkeepsie, New York, US | 3 | 1999–2002 |
| Orrick, MO, US | 1 | 2010 |
| Larangeville, New York, US | 1 | 2007 |