Inventor
Gaurav Verma
Inventor
Sunnyvale, CA, US
Overview
Patents· 41 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
G01RMeasuring electric variables12%
G06FElectric digital data processing12%
H04LTransmission of digital information, e.g. telegraphic communication10%
H04WWireless communication networks6%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices5%
Y10TTechnical subjects covered by former us classification5%
B01JChemical or physical processes, e.g. catalysis or colloid chemistry4%
G01NInvestigating or analysing materials by determining their chemical or physical properties4%
H10DInorganic electric semiconductor devices4%
PatentTitleYear
11,132,339Synchronous replication for synchronous mirror copy guarantee202111,122,090Dynamic application-level compliance enforcement202111,110,419System and method for synthesizing polymeric capsules for water softening202111,108,628Linking multiple enrollments on a client device202111,062,085Goal-driven authoring assistance using causal stylistic prescriptions202111,020,320Pill dispenser for refrigerator appliance202110,999,329Network access by applications in an enterprise managed device system202110,846,466Digital document update using static and transient tags202010,819,842Providing on-demand access to a restricted resource of a user device202010,673,951Migration between device-management services202010,659,294Linking multiple enrollments on a client device202010,560,482Network access by applications in an enterprise managed device system202010,489,498Digital document update201910,454,761Migration of managed devices to utilize management platform features201910,387,593Code coverage reconstruction201910,380,296Connecting designs in mixed language environments201910,380,283Functional verification with machine learning201910,360,332Handling blind statements in mixed language environments20199,960,312Apparatus and methods for fast chemical electrodeposition for fabrication of solar cells20189,164,517'Maintaining flow rate of a fluid'20158,633,039'Methods of combinatorial processing for screening multiple samples on a semiconductor substrate'20148,603,628'Turbine blade protective barrier'20138,343,327'Apparatus and methods for fast chemical electrodeposition for fabrication of solar cells'20138,220,502'Measuring volume of a liquid dispensed into a vessel'20128,143,619'Methods of combinatorial processing for screening multiple samples on a semiconductor substrate'20128,102,408'Computer-implemented methods and systems for determining different process windows for a wafer printing process for different reticle designs'20128,037,894'Maintaining flow rate of a fluid'20117,962,863'Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer'20117,824,935'Methods of combinatorial processing for screening multiple samples on a semiconductor substrate'20107,689,966'Methods, systems, and carrier media for evaluating reticle layout data'20107,493,590'Process window optical proximity correction'20097,280,945'Apparatus and methods for detection of systematic defects'20077,198,963'Methodologies for efficient inspection of test structures using electron beam scanning and step and repeat systems'20077,067,335'Apparatus and methods for semiconductor IC failure detection'20066,995,393'Apparatus and methods for semiconductor IC failure detection'20066,861,666'Apparatus and methods for determining and localization of failures in test structures using voltage contrast'20056,732,002'Apparatus and methods for predicting multiple product chip yields through critical area matching'20046,642,726'Apparatus and methods for reliable and efficient detection of voltage contrast defects'20036,387,803'Method for forming a silicide region on a silicon body'20026,300,208'Methods for annealing an integrated device using a radiant energy absorber layer'20016,297,135'Method for forming silicide regions on an integrated device'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2002Based in Palo Alto, CA, US· patent location history
2003–2007Based in Atherton, CA, US· patent location history
2005–2012Patents assigned to KLA TENCOR TECH CORP (8)· patent assignee history
2009–2018Based in Sunnyvale, CA, US· patent location history
2010–2015Patents assigned to INTERMOLECULAR INC (6)· patent assignee history
2012–2018Patents assigned to VERMA GAURAV (7)· patent assignee history
2019–2021Patents assigned to VMWARE INC (8)· patent assignee history
2019Patents assigned to MENTOR GRAPHICS CORP (4)· patent assignee history
2019–2021Based in Bangalore, IN· patent location history
2019Based in Fremont, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| KLA TENCOR TECH CORP | 8 | 2005–2012 |
| VMWARE INC | 8 | 2019–2021 |
| VERMA GAURAVself | 7 | 2012–2018 |
| INTERMOLECULAR INC | 6 | 2010–2015 |
| MENTOR GRAPHICS CORP | 4 | 2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sunnyvale, California, US | 11 | 2009–2018 |
| Bangalore, IN | 9 | 2019–2021 |
| Atherton, California, US | 7 | 2003–2007 |
| Fremont, California, US | 4 | 2019 |
| Palo Alto, California, US | 3 | 2001–2002 |