Inventor

John Edward Derrick

Inventor

Round Rock, TX, US

Overview

20→

Patents

1997–2011

Patent span

Physics

Primary field (CPC G)

Patents· 20 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing100%

PatentTitleYear

8,065,685'Method, system and apparatus for a transformation engine for use in the processing of structured documents'2011 6,574,727'Method and apparatus for instruction sampling for performance monitoring and debug'2003 6,442,675'Compressed string and multiple generation engine'2002 6,430,678'Scoreboard mechanism for serialized string operations utilizing the XER'2002 6,425,069'Optimization of instruction stream execution that includes a VLIW dispatch group'2002 6,385,719'Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor'2002 6,345,356'Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs'2002 6,336,182'System and method for utilizing a conditional split for aligning internal operation (IOPs) for dispatch'2002 6,321,380'Method and apparatus for modifying instruction operations in a processor'2001 6,304,959'Simplified method to generate BTAGs in a decode unit of a processing system'2001 6,289,428'Superscaler processor and method for efficiently recovering from misaligned data addresses'2001 6,286,094'Method and system for optimizing the fetching of dispatch groups in a superscalar processor'2001 6,240,507'Mechanism for multiple register renaming and method therefor'2001 5,983,025'Computer system buffers for providing concurrency and avoid deadlock conditions between CPU accesses, local bus accesses, and memory accesses'1999 5,906,659'Computer system buffers for providing concurrency between CPU accesses, local bus accesses, and memory accesses'1999 5,890,216'Apparatus and method for decreasing the access time to non-cacheable address space in a computer system'1999 5,872,980'Semaphore access control buffer and method for accelerated semaphore operations'1999 5,787,486'Bus protocol for locked cycle cache hit'1998 5,704,058'Cache bus snoop protocol for optimized multiprocessor computer system'1997 5,659,710'Cache coherency method and system employing serially encoded snoop responses'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2003Patents assigned to IBM (18)· patent assignee history

1997–1999Based in Milton, VT, US· patent location history

2001–2003Based in Round Rock, TX, US· patent location history

2011Patents assigned to CAHOON BRENDON D (1)· patent assignee history

2011Patents assigned to CERMAK DANIEL M (1)· patent assignee history

2011Patents assigned to DERRICK JOHN E (1)· patent assignee history

2011Patents assigned to DOBBS BRYAN (1)· patent assignee history

2011Based in Austin, TX, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	18	1997–2003
CAHOON BRENDON D	1	2011
CERMAK DANIEL M	1	2011
DERRICK JOHN Eself	1	2011
DOBBS BRYAN	1	2011

Locations

Location	Patents	Span
Round Rock, Texas, US	12	2001–2003
Milton, VT, US	7	1997–1999
Austin, Texas, US	1	2011