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Inventor

Sriram Madhavan

Inventor
Santa Clara, CA, US

Overview

13→
Patents
2003–2021
Patent span
Physics
Primary field (CPC G)

Patents· 13 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing24%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
Y02PClimate change mitigation technologies in the production or processing of goods10%
F01NGas-flow silencers or exhaust apparatus for machines or engines in general7%
F02DControlling combustion engines7%
H10DInorganic electric semiconductor devices7%
Y02TClimate change mitigation technologies related to transportation7%
G01RMeasuring electric variables3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
PatentTitleYear
10,968,803Systems and methods for idle fuel economy mode202110,392,990Systems and methods for idle fuel economy mode201910,372,871IC layout post-decomposition mask allocation optimization201910,095,826Feed-forward for silicon inspections (DFM2CFM : design to silicon) and feed-back for weakpoint predictor decks (CFM2DFM : silicon to design) guided by marker classification, sampling, and higher dimensional analysis201810,055,535Method, system and program product for identifying anomalies in integrated circuit design layouts20188,918,745'Stitch insertion for reducing color density differences in double patterning technology (DPT)'20148,745,553'Method and apparatus for applying post graphic data system stream enhancements'20148,656,336'Pattern based method for identifying design for manufacturing improvement in a semiconductor device'20148,516,407'Methods for quantitatively evaluating the quality of double patterning technology-compliant layouts'20138,293,606'Body tie test structure for accurate body effect measurement'20127,880,229'Body tie test structure for accurate body effect measurement'20117,804,317'Test device for determining charge damage to a transistor'20106,534,378'Method for forming an integrated circuit device'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003Based in Milpitas, CA, US· patent location history
2010–2019Based in Santa Clara, CA, US· patent location history
2011–2019Patents assigned to GLOBALFOUNDRIES INC (8)· patent assignee history
2012–2014Patents assigned to MADHAVAN SRIRAM (5)· patent assignee history
2013–2014Patents assigned to CAPODIECI LUIGI (2)· patent assignee history
2014Patents assigned to MALIK SHOBHIT (2)· patent assignee history
2019–2021Patents assigned to CUMMINS INC (2)· patent assignee history
2019–2021Based in Columbus, IN, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
GLOBALFOUNDRIES INC82011–2019
MADHAVAN SRIRAMself52012–2014
CAPODIECI LUIGI22013–2014
CUMMINS INC22019–2021
MALIK SHOBHIT22014
Locations
LocationPatentsSpan
Santa Clara, California, US102010–2019
Columbus, IN, US22019–2021
Milpitas, California, US12003