LexDanaLexDanabeta
Inventor

Bernard Aspar

Inventor
Rives, FR

Overview

70→
Patents
2000–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 70 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1025%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
Y10TTechnical subjects covered by former us classification9%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems6%
H10DInorganic electric semiconductor devices5%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
B81BMicrostructural devices or systems, e.g. micromechanical devices2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
H01LSemiconductor devices1%
PatentTitleYear
11,043,756Structure for radio frequency applications202110,826,459Heterostructure and method of fabrication20209,728,458'Methods for fabrication of semiconductor structures using laser lift-off process, and related semiconductor structures'20179,511,996'Methods of forming semiconductor structures including MEMS devices and integrated circuits on common sides of substrates, and related structures and devices'20169,481,566'Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices'20168,722,515'Process of treating defects during the bonding of wafers'20148,679,946'Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate'20148,628,674'Method for trimming a structure obtained by the assembly of two plates'20148,609,514'Process for the transfer of a thin film comprising an inclusion creation step'20138,575,010'Method for fabricating a semiconductor substrate'20138,530,334'Process of treating defects during the bonding of wafers'20138,481,409'Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate'20138,475,693'Methods of making substrate structures having a weakened intermediate layer'20138,470,712'Process for the transfer of a thin film comprising an inclusion creation step'20138,329,048'Method for trimming a structure obtained by the assembly of two plates'20128,298,915'Method of transferring a circuit onto a ground plane'20128,268,703'Surface roughening process'20128,232,130'Process for assembling wafers by means of molecular adhesion'20128,193,069'Stacked structure and production method thereof'20128,158,487'Annealing process for annealing a structure'20128,101,503'Method of producing a thin layer of semiconductor material'20128,044,465'Method for producing partial SOI structures comprising zones connecting a superficial layer and a substrate'20117,902,038'Detachable substrate with controlled mechanical strength and method of producing same'20117,883,994'Process for the transfer of a thin film'20117,807,482'Method for transferring wafers'20107,807,548'Process of forming and controlling rough interfaces'20107,737,000'Process for the collective fabrication of microstructures consisting of superposed elements'20107,713,369'Detachable substrate or detachable structure and method for the production thereof'20107,709,305'Method for producing partial SOI structures comprising zones connecting a superficial layer and a substrate'20107,615,463'Method for making thin layers containing microcomponents'20097,498,234'Method of producing a thin layer of semiconductor material'20097,498,245'Embrittled substrate and method for making same'20097,494,897'Method of producing mixed substrates and structure thus obtained'20097,368,030'Intermediate suction support and its utilisation for producing a thin film structure'20087,264,996'Method for separating wafers bonded together to form a stacked structure'20077,258,743'Composite structure with a uniform crystal orientation and the method of controlling the crystal orientation of one such structure'20077,238,598'Formation of a semiconductor substrate that may be dismantled and obtaining a semiconductor element'20077,229,899'Process for the transfer of a thin film'20077,205,211'Method for handling semiconductor layers in such a way as to thin same'20077,067,396'Method of producing a thin layer of semiconductor material'20067,060,590'Layer transfer method'20067,029,548'Method for cutting a block of material and forming a thin film'20066,974,759'Method for making a stacked comprising a thin film adhering to a target substrate'20056,959,863'Method for selectively transferring at least an element from an initial support onto a final support'20056,946,365'Method for producing a thin film comprising introduction of gaseous species'20056,939,782'Method for producing thin layers on a specific support and an application thereof'20056,913,971'Layer transfer methods'20056,909,445'High density element structure formed by assembly of layers and method for making same'20056,853,414'Flat liquid crystal, screen operating in reflective mode and method for manufacturing this screen'20056,821,376'Method for separating two elements and a device therefor'20046,809,044'Method for making a thin film using pressurization'20046,809,009'Method of producing a thin layer of semiconductor material'20046,808,967'Method for producing a buried layer of material in another material'20046,756,285'Multilayer structure with controlled internal stresses and making same'20046,756,286'Method for transferring a thin film comprising a step of generating inclusions'20046,593,036'Structure for a reflection lithography mask and method for making same'20036,465,327'Method for producing a thin membrane and resulting structure with membrane'20026,429,094'Treatment process for molecular bonding and unbonding of two structures'20026,403,450'Heat treatment method for semiconductor substrates'20026,362,077'Structure comprising a thin layer of material made up of conductive zones and insulating zones and a method of manufacturing such a structure'20026,335,258'Method for making a thin film on a support and resulting structure including an additional thinning stage before heat treatment causes micro-cavities to separate substrate element'20026,316,333'Method for obtaining a thin film in particular semiconductor, comprising a protected ion zone and involving an ion implantation'20016,303,468'Method for making a thin film of solid material'20016,225,192'Method of producing a thin layer of semiconductor material'20016,204,079'Selective transfer of elements from one support to another support'20016,197,695'Process for the manufacture of passive and active components on the same insulating substrate'20016,190,998'Method for achieving a thin film of solid material and applications of this method'20016,110,802'Process for producing a structure with a low dislocation density comprising an oxide layer buried in a semiconductor substrate'20006,103,597'Method of obtaining a thin film of semiconductor material'20006,020,252'Method of producing a thin layer of semiconductor material'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2014Patents assigned to COMMISSARIAT ENERGIE ATOMIQUE (50)· patent assignee history
2000–2014Based in Rives, FR· patent location history
2009–2021Patents assigned to SOITEC SILICON ON INSULATOR (19)· patent assignee history
2012–2013Patents assigned to ASPAR BERNARD (12)· patent assignee history
2012–2013Patents assigned to MORICEAU HUBERT (4)· patent assignee history
2012–2013Patents assigned to BRUEL MICHEL (3)· patent assignee history
2012–2021Based in Saint Ismier, FR· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
COMMISSARIAT ENERGIE ATOMIQUE502000–2014
SOITEC SILICON ON INSULATOR192009–2021
ASPAR BERNARDself122012–2013
MORICEAU HUBERT42012–2013
BRUEL MICHEL32012–2013
Locations
LocationPatentsSpan
Rives, FR592000–2014
Saint Ismier, FR112012–2021