Inventor
Daniel P. Wilde
Inventor
Cedar Park, TX, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Tprimary
G06TImage data processing or generation, in general68%
G06FElectric digital data processing21%
G09GArrangements or circuits for control of indicating devices using static means to present variable information12%
PatentTitleYear
10,884,487Position based energy minimizing function20219,721,381'System, method, and computer program product for discarding pixel samples'20178,233,004'Color-compression using automatic reduction of multi-sampled pixels'20127,880,747'Blend optimizations that are conformant to floating-point rules'20117,725,688'System and method for storing states used to configure a processing pipeline in a graphics processing unit'20107,692,659'Color-compression using automatic reduction of multi-sampled pixels'20107,382,368'Planar z representation for z compression'20086,366,290'Dynamically selectable texture filter for a software graphics engine'20026,333,746'Auto level of detail texture mapping for a software graphics engine'20016,292,191'Dynamically selectable MIP map blending for a software graphics engine'20016,252,606'Error correction in a graphics processor'20016,204,863'Method for dynamic XY tiled texture caching'20016,157,386'MIP map blending in a graphics processor'20006,130,674'Dynamically selectable texture filter for computer graphics'20006,088,016'Dithering method and apparatus using ramp probability logic'20006,061,510'Local bus interface'20006,052,127'Circuit for determining non-homogenous second order perspective texture mapping coordinates using linear interpolation'20006,008,796'Software-based dithering method and apparatus using ramp probability logic'19995,986,663'Auto level of detail-based MIP mapping in a graphics processor'19995,940,090'Method and apparatus for internally caching the minimum and maximum XY pixel address values in a graphics subsystem'19995,936,635'System and method of rendering polygons into a pixel grid'19995,929,869'Texture map storage with UV remapping'19995,887,157'Local bus interface'19995,844,576'Tiled linear host texture storage'19985,828,382'Apparatus for dynamic XY tiled texture caching'19985,798,763'Object referenced memory segmentation'19985,715,421'Apparatus and method of addressing paged mode memory including adjacent page precharging'19985,649,162'Local bus interface'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–1999Patents assigned to MICRON ELECTRONICS INC (2)· patent assignee history
1997–2000Based in Red Wing, MN, US· patent location history
1998–2002Patents assigned to CIRRUS LOGIC INC (15)· patent assignee history
1998–2017Based in Cedar Park, TX, US· patent location history
1998Based in Redwing, MN, US· patent location history
1999–2000Patents assigned to S3 INC (2)· patent assignee history
2008–2017Patents assigned to NVIDIA CORP (6)· patent assignee history
2012Patents assigned to FRENCH MARK J (1)· patent assignee history
2021Based in Cambridge, GB· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CIRRUS LOGIC INC | 15 | 1998–2002 |
| NVIDIA CORP | 6 | 2008–2017 |
| MICRON ELECTRONICS INC | 2 | 1997–1999 |
| S3 INC | 2 | 1999–2000 |
| FRENCH MARK J | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cedar Park, Texas, US | 23 | 1998–2017 |
| Red Wing, Minnesota, US | 3 | 1997–2000 |
| Cambridge, GB | 1 | 2021 |
| Redwing, Minnesota, US | 1 | 1998 |