Inventor

David Mui

Inventor

Fremont, CA, US

Overview

2000–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 66 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1031%

G06FElectric digital data processing17%

C11DDetergent compositions9%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests9%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices7%

B08BCleaning in general5%

H01LSemiconductor devices4%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%

H01JElectric discharge tubes or discharge lamps2%

G01RMeasuring electric variables2%

PatentTitleYear

10,861,719Method and apparatus for processing wafer-shaped articles2020 10,720,343Method and apparatus for processing wafer-shaped articles2020 10,679,871Method and apparatus for processing wafer-shaped articles2020 10,446,416Method and apparatus for processing wafer-shaped articles2019 9,772,851'Retrieving instructions of a single branch, backwards short loop from a local loop buffer or virtual loop buffer'2017 9,632,788'Buffering instructions of a single branch, backwards short loop within a virtual loop buffer'2017 9,395,995'Retrieving instructions of a single branch, backwards short loop from a virtual loop buffer'2016 9,159,593'Method of particle contaminant removal'2015 9,069,563'Reducing store-hit-loads in an out-of-order processor'2015 9,052,910'Efficiency of short loop instruction fetch'2015 8,968,485'Apparatus and methods for processing a substrate'2015 8,943,299'Operating a stack of information in an information handling system'2015 8,758,522'Method and apparatus for removing contaminants from substrate'2014 8,617,993'Method of reducing pattern collapse in high aspect ratio nanostructures'2013 8,611,368'Controlling bandwidth reservations method and apparatus'2013 8,601,639'Apparatus for application of two-phase contaminant removal medium'2013 8,585,825'Acoustic assisted single wafer wet clean for semiconductor wafer process'2013 8,480,809'Methods for application of two-phase contaminant removal medium'2013 8,483,227'Controlling bandwidth reservations method and apparatus'2013 8,314,055'Materials and systems for advanced substrate cleaning'2012 8,227,394'Composition of a cleaning material for particle removal'2012 8,226,775'Methods for particle removal by single-phase and two-phase media'2012 8,211,846'Materials for particle removal by single-phase and two-phase media'2012 8,105,997'Composition and application of a two-phase contaminant removal medium'2012 8,084,406'Apparatus for particle removal by single-phase and two-phase media'2011 7,967,019'Method and apparatus for removing contaminants from substrate'2011 7,900,027'Scalable link stack control method with full support for speculative operations'2011 7,877,523'Apparatus, computer program product, and system for completing a plurality of chained list DMA commands that include a fenced list DMA command element'2011 7,779,232'Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches'2010 7,644,198'DMAC translation mechanism'2010 7,529,799'Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system'2009 7,512,722'Method for completing a plurality of chained list DMA commands that include a fenced list DMA command element'2009 7,498,106'Method and apparatus for controlling etch processes during fabrication of semiconductor devices'2009 7,482,178'Chamber stability monitoring using an integrated metrology tool'2009 7,444,435'Non-fenced list DMA command mechanism'2008 7,262,865'Method and apparatus for controlling a calibration cycle or a metrology tool'2007 7,250,373'Method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate'2007 7,203,811'Non-fenced list DMA command mechanism'2007 7,107,376'Systems and methods for bandwidth shaping'2006 7,094,613'Method for controlling accuracy and repeatability of an etch process'2006 6,960,416'Method and apparatus for controlling etch processes during fabrication of semiconductor devices'2005 6,924,191'Method for fabricating a gate structure of a field effect transistor'2005 6,924,088'Method and system for realtime CD microloading control'2005 6,911,399'Method of controlling critical dimension microloading of photoresist trimming process by selective sidewall polymer deposition'2005 6,858,361'Methodology for repeatable post etch CD in a production tool'2005 6,849,151'Monitoring substrate processing by detecting reflectively diffracted light'2005 6,822,486'Multiplexer methods and apparatus'2004 6,703,315'Method of providing a shallow trench in a deep-trench device'2004 6,699,399'Self-cleaning etch process'2004 6,677,242'Integrated shallow trench isolation approach'2004 6,653,237'High resist-selectivity etch for silicon trench etch applications'2003 6,632,321'Method and apparatus for monitoring and controlling wafer fabrication process'2003 6,589,879'Nitride open etch process based on trifluoromethane and sulfur hexafluoride'2003 6,589,715'Process for depositing and developing a plasma polymerized organosilicon photoresist film'2003 6,566,270'Integration of silicon etch and chamber cleaning processes'2003 6,510,471'Method for choosing device among plurality of devices based on coherncy status of device\'s data and if device supports higher-performance transactions'2003 6,484,220'Transfer of data between processors in a multi-processor system'2002 6,458,671'Method of providing a shallow trench in a deep-trench device'2002 6,449,698'Method and system for bypass prefetch data path'2002 6,317,811'Method and system for reissuing load requests in a multi-stream prefetch design'2001 6,238,844'Process for depositing a plasma polymerized organosilicon photoresist film'2001 6,235,643'Method for etching a trench having rounded top and bottom corners in a silicon substrate'2001 6,180,533'Method for etching a trench having rounded top corners in a silicon substrate'2001 6,136,211'Self-cleaning etch process'2000 6,134,684'Method and system for error detection in test units utilizing pseudo-random data'2000 6,037,265'Etchant gas and a method for etching transistor gates'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2009Patents assigned to APPLIED MATERIALS INC (23)· patent assignee history

2000–2017Patents assigned to IBM (22)· patent assignee history

2000–2017Based in Round Rock, TX, US· patent location history

2000–2004Based in San Jose, CA, US· patent location history

2000–2003Based in Santa Clara, CA, US· patent location history

2005–2020Based in Fremont, CA, US· patent location history

2011–2015Patents assigned to LAM RES CORP (13)· patent assignee history

2011–2015Patents assigned to MENDIRATTA ARJUN (10)· patent assignee history

2012–2017Patents assigned to MUI DAVID (15)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
APPLIED MATERIALS INC	23	2000–2009
IBM	22	2000–2017
MUI DAVIDself	15	2012–2017
LAM RES CORP	13	2011–2015
MENDIRATTA ARJUN	10	2011–2015

Locations

Location	Patents	Span
Fremont, California, US	29	2005–2020
Round Rock, Texas, US	23	2000–2017
San Jose, California, US	10	2000–2004
Santa Clara, California, US	4	2000–2003