Inventor
Gary E. Strait
Inventor
Poughkeepsie, NY, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing72%
H03MCoding9%
G11CStatic stores6%
B63BShips or other waterborne vessels3%
B63CLaunching, hauling-out, or dry-docking of vessels3%
F16LPipes3%
H04LTransmission of digital information, e.g. telegraphic communication3%
PatentTitleYear
10,572,304Dual/multi-mode processor pipelines sampling202010,528,253Increased bandwidth of ordered stores in a non-uniform memory subsystem202010,331,576Deadlock avoidance in a multi-processor computer system with extended cache line locking201910,176,013Dual/multi-mode processor pipeline sampling201910,042,554Increased bandwidth of ordered stores in a non-uniform memory subsystem20189,858,190'Maintaining order with parallel access data streams'20189,299,456'Matrix and compression-based error detection'20169,268,660'Matrix and compression-based error detection'20169,065,481'Bad wordline/array detection in memory'20158,914,708'Bad wordline/array detection in memory'20148,850,129'Memory ordered store system in a multiprocessor computer system'20148,656,228'Memory error isolation and recovery in a multiprocessor computer system'20148,539,158'Merging data in an L2 cache memory'20138,250,305'Method, system and computer program product for data buffers partitioned from a cache array'20128,090,883'Method, system and computer program product for enhanced shared store buffer management scheme with limited resources for optimized performance'20128,055,753'Peer to peer job monitoring and control in grid computing systems'20118,006,039'Method, system, and computer program product for merging data'20117,886,089'Method, system and computer program product for enhanced shared store buffer management scheme for differing buffer sizes with limited resources for optimized performance'20117,478,185'Directly initiating by external adapters the setting of interruption initiatives'20097,383,336'Distributed shared resource management'20087,085,897'Memory management for a symmetric multiprocessor computer system'20066,163,857'Computer system UE recovery logic'20006,151,655'Computer system deadlock request resolution using timed pulses'20006,073,182'Method of resolving deadlocks between competing requests in a multiprocessor using global hang pulse logic'20005,355,818'Portable inspection equipment for ocean going vessels'19944,564,944'Error correcting scheme'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986–2020Patents assigned to IBM (25)· patent assignee history
1986–2020Based in Poughkeepsie, NY, US· patent location history
1994Based in San Pedro, CA, US· patent location history
2009Based in LaGrange, NY, US· patent location history
2012–2014Patents assigned to STRAIT GARY E (6)· patent assignee history
2012–2014Patents assigned to SONNELITTER III ROBERT J (3)· patent assignee history
2012–2014Patents assigned to CHECK MARK A (2)· patent assignee history
2012–2014Patents assigned to MAK PAK-KIN (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 25 | 1986–2020 |
| STRAIT GARY Eself | 6 | 2012–2014 |
| SONNELITTER III ROBERT J | 3 | 2012–2014 |
| CHECK MARK A | 2 | 2012–2014 |
| MAK PAK-KIN | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 24 | 1986–2020 |
| LaGrange, New York, US | 1 | 2009 |
| San Pedro, California, US | 1 | 1994 |