Inventor
Ely K. Tsern
Inventor
Los Altos, CA, US
Overview
Patents· 211 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores36%
G06FElectric digital data processing34%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
H04LTransmission of digital information, e.g. telegraphic communication4%
H05KPrinted circuits3%
H01LSemiconductor devices3%
H10BElectronic memory devices2%
H03MCoding2%
H03KPulse technique1%
PatentTitleYear
11,043,258Memory system topologies including a memory die stack202111,011,248DRAM retention test method for dynamic error correction202111,010,263High performance persistent memory202110,964,361Memory component with adjustable core-to-interface data rate ratio202110,846,252Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules202010,817,419Memory controller supporting nonvolatile physical memory202010,811,080Memory component with pattern register circuitry to provide data patterns for calibration202010,804,139Semiconductor system202010,706,910Memory controller202010,700,671Data transmission using delayed timing signals202010,672,458Memory system topologies including a buffer device and an integrated circuit memory device202010,664,344Memory repair method and apparatus based on error code tracking202010,650,872Memory component with multiple command/address sampling modes202010,621,023Memory controller with error detection and retry modes of operation202010,592,120Memory system with threaded transaction support202010,561,253Adaptive sleep system using data analytics and learning techniques to improve individual sleep conditions202010,535,398Memory system topologies including a buffer device and an integrated circuit memory device202010,497,457DRAM retention test method for dynamic error correction201910,381,067Memory system topologies including a buffer device and an integrated circuit memory device201910,360,972Memories and memory components with interconnected and redundant data interfaces201910,236,051Memory controller201910,223,309Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules201910,210,080Memory controller supporting nonvolatile physical memory201910,191,822High performance persistent memory201910,192,609Memory component with pattern register circuitry to provide data patterns for calibration201910,170,170Memory control component with dynamic command/address signaling rate201910,095,565Memory controller with error detection and retry modes of operation201810,084,644Portable universal personal storage, entertainment, and communication device201810,026,666Stacked die package with aligned active and passive through-silicon vias20189,865,329'Memory system topologies including a buffer device and an integrated circuit memory device'20189,847,248Method of making a stacked device assembly20179,842,630'Memory component with adjustable core-to-interface data rate ratio'20179,843,315'Data transmission using delayed timing signals'20179,836,348Memory repair method and apparatus based on error code tracking20179,824,036'Memory systems with multiple modules supporting simultaneous access responsive to common memory commands'20179,818,463'Memory control component with inter-rank skew tolerance'20179,741,424'Memory controller'20179,721,642'Memory component with pattern register circuitry to provide data patterns for calibration'20179,691,504'DRAM retention test method for dynamic error correction'20179,665,430'Memory system with error detection and retry modes of operation'20179,563,583'Memory system topologies including a buffer device and an integrated circuit memory device'20179,563,597'High capacity memory systems with inter-rank skew tolerance'20179,515,008'Techniques for interconnecting stacked dies using connection sites'20169,472,262'Memory controller'20169,459,960'Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation'20169,430,324'Memory repair method and apparatus based on error code tracking'20169,411,678'DRAM retention monitoring method for dynamic error correction'20169,390,782'Memory with refresh logic to accommodate low-retention storage rows'20169,367,248'Memory component with pattern register circuitry to provide data patterns for calibration'20169,311,976'Memory module'20169,298,609'Memory controller supporting nonvolatile physical memory'20169,287,239'Techniques for interconnecting stacked dies using connection sites'20169,274,892'Memory chip with error detection and retry modes of operation'20169,256,376'Methods and circuits for dynamically scaling DRAM power and performance'20169,257,151'Printed-circuit board supporting memory systems with multiple data-bus configurations'20169,257,159'Low power memory device'20169,141,479'Memory system with error detection and retry modes of operation'20159,123,433'Memory component with pattern register circuitry to provide data patterns for calibration'20159,117,035'Memory system topologies including a buffer device and an integrated circuit memory device'20159,099,194'Memory component with pattern register circuitry to provide data patterns for calibration'20159,053,778'Memory controller that enforces strobe-to-strobe timing offset'20158,930,779'Bit-replacement technique for DRAM error correction'20158,918,703'Memory system with error detection and retry modes of operation'20148,824,224'Frequency-agile strobe window generation'20148,811,095'Methods and circuits for dynamically scaling DRAM power and performance'20148,769,234'Memory modules and devices supporting configurable data widths'20148,760,944'Memory component that samples command/address signals in response to both edges of a clock signal'20148,756,368'Memory controller with refresh logic to accommodate low-retention storage rows in a memory device'20148,756,395'Controlling DRAM at time DRAM ready to receive command when exiting power down'20148,749,042'Process for making a semiconductor system'20148,745,315'Memory Systems and methods supporting volatile and wear-leveled nonvolatile physical memory'20148,717,837'Memory module'20148,677,285'User interface of a small touch sensitive display for an electronic data and communication device'20148,625,371'Memory component with terminated and unterminated signaling inputs'20148,595,336'Portable universal personal storage, entertainment, and communication device'20138,583,071'Methods and circuits for detecting and reporting high-energy particles using mobile phones and other portable computing devices'20138,542,787'Phase adjustment apparatus and method for a memory device signaling system'20138,539,152'Memory system topologies including a buffer device and an integrated circuit memory device'20138,537,601'Memory controller with selective data transmission delay'20138,462,566'Memory module with termination component'20138,412,906'Memory apparatus supporting multiple width configurations'20138,395,951'Memory controller'20138,391,039'Memory module with termination component'20138,380,927'Upgradable system with reconfigurable interconnect'20138,359,445'Method and apparatus for signaling between devices of a memory system'20138,344,998'Gesture-based power management of a wearable portable electronic device with display'20138,320,202'Clocked memory system with termination component'20128,305,839'Memory device having multiple power modes'20128,296,540'Method and apparatus for adjusting the performance of a synchronous memory system'20128,295,107'Asynchronous pipelined memory access'20128,278,964'Method and apparatus for test and characterization of semiconductor components'20128,248,884'Method of controlling a memory device having multiple power modes'20128,212,650'Situationally aware and self-configuring electronic data and communication device'20128,214,616'Memory controller device having timing offset capability'20128,194,493'Low power memory device'20128,127,152'Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit mode'20128,112,608'Variable-width memory'20128,108,607'Memory system topologies including a buffer device and an integrated circuit memory device'20128,059,476'Control component for controlling a delay interval within a memory component'20117,989,265'Process for making a semiconductor system having devices that have contacts on top and bottom surfaces of each device'20117,986,584'Memory device having multiple power modes'20117,965,567'Phase adjustment apparatus and method for a memory device signaling system'20117,916,570'Low power memory device'20117,831,882'Memory system with error detection and retry modes of operation'20107,830,735'Asynchronous, high-bandwidth memory component using calibrated timing elements'20107,764,095'Clock distribution network supporting low-power mode'20107,734,866'Memory with address-differentiated refresh rate to accommodate low-retention storage rows'20107,729,151'System including a buffered memory module'20107,701,045'Point-to-point connection topology for stacked devices'20107,685,364'Memory system topologies including a buffer device and an integrated circuit memory device'20107,668,276'Phase adjustment apparatus and method for a memory device signaling system'20107,660,183'Low power memory device'20107,626,880'Memory device having a read pipeline and a delay locked loop'20097,610,447'Upgradable memory system with reconfigurable interconnect'20097,592,824'Method and apparatus for test and characterization of semiconductor components'20097,581,121'System for a memory device having a power down mode and method'20097,577,789'Upgradable memory system with reconfigurable interconnect'20097,574,616'Memory device having a power down exit register'20097,571,330'System and module including a memory device having a power down mode'20097,565,479'Memory with refresh cycle donation to accommodate low-retention-storage rows'20097,562,271'Memory system topologies including a buffer device and an integrated circuit memory device'20097,536,494'Expandable slave device system with buffered subsystems'20097,529,141'Asynchronous, high-bandwidth memory component using calibrated timing elements'20097,526,597'Buffered memory having a control bus and dedicated data lines'20097,523,248'System having a controller device, a buffer device and a plurality of memory devices'20097,484,064'Method and apparatus for signaling between devices of a memory system'20097,464,225'Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology'20087,454,555'Apparatus and method including a memory device having multiple sets of memory banks with duplicated data emulating a fast access time, fixed latency memory device'20087,444,577'Memory device testing to support address-differentiated refresh rates'20087,404,032'Configurable width buffered module having switch elements'20087,398,413'Memory device signaling system and method with independent timing calibration for parallel signal paths'20087,368,961'Clock distribution network supporting low-power mode'20087,363,422'Configurable width buffered module'20087,362,626'Asynchronous, high-bandwidth memory component using calibrated timing elements'20087,356,639'Configurable width buffered module having a bypass circuit'20087,353,357'Apparatus and method for pipelined memory operations'20087,349,279'Memory Device Having a Configurable Oscillator for Refresh Operation'20087,337,294'Method and apparatus for adjusting the performance of a synchronous memory system'20087,330,951'Apparatus and method for pipelined memory operations'20087,320,047'System having a controller device, a buffer device and a plurality of memory devices'20087,320,082'Power control system for synchronous memory device'20087,266,634'Configurable width buffered module having flyby elements'20077,263,149'Apparatus and method for generating a distributed clock signal'20077,225,292'Memory module with termination component'20077,225,311'Method and apparatus for coordinating memory operations among diversely-located memory components'20077,222,209'Expandable slave device system'20077,210,016'Method, system and memory controller utilizing adjustable write data delay settings'20077,209,397'Memory device with clock multiplier circuit'20077,206,897'Memory module having an integrated circuit buffer device'20077,206,896'Integrated circuit buffer device'20077,200,710'Buffer device and method of operation in a buffer device'20077,200,055'Memory module with termination component'20077,177,998'Method, system and memory controller utilizing adjustable read data delay settings'20077,170,314'Multiple channel modules and bus systems using same'20077,149,856'Method and apparatus for adjusting the performance of a synchronous memory system'20067,142,475'Memory device having a configurable oscillator for refresh operation'20067,073,035'Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules'20067,062,597'Integrated circuit buffer device'20067,051,151'Integrated circuit buffer device'20067,039,782'Memory system with channel multiplexing of multiple memory devices'20067,017,002'System featuring a master device, a buffer device and a plurality of integrated circuit memory devices'20067,010,642'System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices'20067,003,618'System featuring memory modules that include an integrated circuit buffer devices'20067,003,639'Memory controller with power management logic'20067,000,062'System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices'20066,963,956'Apparatus and method for pipelined memory operations'20056,961,831'Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules'20056,934,201'Asynchronous, high-bandwidth memory component using calibrated timing elements'20056,920,540'Timing calibration apparatus and method for a memory device signaling system'20056,898,085'Multiple channel modules and bus systems using same'20056,842,864'Method and apparatus for configuring access times of memory devices'20056,839,266'Memory module with offset data lines and bit line swizzle configuration'20056,836,521'Apparatus and method for generating a distributed clock signal using gear ratio techniques'20046,832,284'Integrated circuit buffer device'20046,826,657'Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules'20046,788,594'Asynchronous, high-bandwidth memory component using calibrated timing elements'20046,788,593'Asynchronous, high-bandwidth memory component using calibrated timing elements'20046,785,782'Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules'20046,778,458'Dram core refresh with reduced spike current'20046,769,050'Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules'20046,765,800'Multiple channel modules and bus systems using same'20046,754,783'Memory controller with power management logic'20046,718,431'Apparatus and method for pipelined memory operations'20046,708,248'Memory system with channel multiplexing of multiple memory devices'20046,701,446'Power control system for synchronous memory device'20046,687,780'Expandable slave device system'20046,675,272'Method and apparatus for coordinating memory operations among diversely-located memory components'20046,636,935'Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules'20036,597,616'DRAM core refresh with reduced spike current'20036,574,153'Asynchronous, high-bandwidth memory component using calibrated timing elements'20036,553,452'Synchronous memory device having a temperature register'20036,523,089'Memory controller with power management logic'20036,513,103'Method and apparatus for adjusting the performance of a synchronous memory system'20036,502,161'Memory system including a point-to-point linked memory subsystem'20026,396,887'Apparatus and method for generating a distributed clock signal using gear ratio techniques'20026,378,018'Memory device and system including a low power interface'20026,373,768'Apparatus and method for thermal regulation in memory subsystems'20026,370,668'High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes'20026,356,975'Apparatus and method for pipelined memory operations'20026,345,009'Apparatus and method for refreshing subsets of memory devices in a memory system'20026,343,042'DRAM core refresh with reduced spike current'20026,266,292'DRAM core refresh with reduced spike current'20016,263,448'Power control system for synchronous memory device'20016,226,757'Apparatus and method for bus timing compensation'20016,226,754'Apparatus and method for device timing compensation'20016,178,130'Apparatus and method for refreshing subsets of memory devices in a memory system'20016,154,821'Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain'20006,134,172'Apparatus for sharing sense amplifiers between memory banks'20006,075,743'Method and apparatus for sharing sense amplifiers between memory banks'20006,075,744'Dram core refresh with reduced spike current'20006,021,076'Apparatus and method for thermal regulation in memory subsystems'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2021Patents assigned to RAMBUS INC (204)· patent assignee history
2000–2021Based in Los Altos, CA, US· patent location history
2011–2016Patents assigned to TSERN ELY K (27)· patent assignee history
2011–2016Patents assigned to WARE FREDERICK A (23)· patent assignee history
2011–2016Patents assigned to HAMPEL CRAIG E (19)· patent assignee history
2012–2013Patents assigned to PEREGO RICHARD E (11)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| RAMBUS INC | 204 | 2000–2021 |
| TSERN ELY Kself | 27 | 2011–2016 |
| WARE FREDERICK A | 23 | 2011–2016 |
| HAMPEL CRAIG E | 19 | 2011–2016 |
| PEREGO RICHARD E | 11 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Altos, California, US | 211 | 2000–2021 |