Inventor
Joyce C. Liu
Inventor
Hopewell Junction, NY, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%
H10DInorganic electric semiconductor devices29%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H01LSemiconductor devices10%
H10BElectronic memory devices6%
C09GPolishing compositions2%
C23FNon-mechanical removal of metallic material from surface2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
PatentTitleYear
10,446,484Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variability201910,095,115Forming edge etch protection using dual layer of positive-negative tone resists20189,847,290Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variability20179,728,506'Strain engineering devices using partial depth films in through-substrate vias'20179,252,133'Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures'20168,907,494'Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures'20147,858,485'Structure and method for manufacturing trench capacitance'20107,081,393'Reduced dielectric constant spacer materials integration for high speed logic gates'20066,838,347'Method for reducing line edge roughness of oxide material using chemical oxide removal'20056,828,187'Method for uniform reactive ion etching of dual pre-doped polysilicon regions'20046,821,890'Method for improving adhesion to copper'20046,727,589'Dual damascene flowable oxide insulation structure and metallic barrier'20046,720,249'Protective hardmask for producing interconnect structures'20046,703,312'Method of forming active devices of different gatelengths using lithographic printed gate images of same length'20046,518,151'Dual layer hard mask for eDRAM gate etch process'20036,479,884'Interim oxidation of silsesquioxane dielectric for dual damascene process'20026,429,067'Dual mask process for semiconductor devices'20026,348,076'Slurry for mechanical polishing (CMP) of metals and use thereof'20026,348,736'In situ formation of protective layer on silsesquioxane dielectric for dual damascene process'20026,329,280'Interim oxidation of silsesquioxane dielectric for dual damascene process'20016,284,574'Method of producing heat dissipating structure for semiconductor devices'20016,271,595'Method for improving adhesion to copper'20016,221,780'Dual damascene flowable oxide insulation structure and metallic barrier'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2014Patents assigned to IBM (18)· patent assignee history
2001–2004Based in Hopewell Junction, NY, US· patent location history
2003Patents assigned to INFINEON TECHNOLOGIES AG (1)· patent assignee history
2004–2019Based in Carmel, NY, US· patent location history
2016–2019Patents assigned to GLOBALFOUNDRIES INC (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 18 | 2001–2014 |
| GLOBALFOUNDRIES INC | 5 | 2016–2019 |
| INFINEON TECHNOLOGIES AG | 1 | 2003 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hopewell Junction, New York, US | 12 | 2001–2004 |
| Carmel, New York, US | 11 | 2004–2019 |