Inventor

Frederick N. Hause

Inventor

Austin, TX, US

Overview

1986–2007

Patent span

Electricity

Primary field (CPC H)

Patents· 110 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices47%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices5%

B24BMachines, devices, or processes for grinding or polishing1%

G01JMeasurement of intensity, velocity, spectral content, polarisation, phase or pulse characteristics of infrared, visible or ultraviolet light1%

B82YSpecific uses or applications of nanostructures1%

C23CCoating metallic material1%

C30BSingle-crystal growth1%

PatentTitleYear

7,220,655'Method of forming an alignment mark on a wafer, and a wafer comprising same'2007 6,809,032'Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques'2004 6,661,057'Tri-level segmented control transistor and fabrication method'2003 6,555,892'Semiconductor device with reduced line-to-line capacitance and cross talk noise'2003 6,555,479'Method for forming openings for conductive interconnects'2003 6,552,776'Photolithographic system including light filter that compensates for lens error'2003 6,514,858'Test structure for providing depth of polish feedback'2003 6,491,799'Method for forming a thin dielectric layer'2002 6,489,240'Method for forming copper interconnects'2002 6,458,678'Transistor formed using a dual metal process for gate and source/drain region'2002 6,429,052'Method of making high performance transistor with a reduced width gate electrode and device comprising same'2002 6,426,262'Method of analyzing the effects of shadowing of angled halo implants'2002 6,413,846'Contact each methodology and integration scheme'2002 6,410,409'Implanted barrier layer for retarding upward diffusion of substrate dopant'2002 6,410,967'Transistor having enhanced metal silicide and a self-aligned gate electrode'2002 6,403,445'Enhanced trench isolation structure'2002 6,380,055'Dopant diffusion-retarding barrier region formed within polysilicon gate layer'2002 6,376,350'Method of forming low resistance gate electrode'2002 6,372,588'Method of making an IGFET using solid phase diffusion to dope the gate, source and drain'2002 6,358,826'Device improvement by lowering LDD resistance with new spacer/silicide process'2002 6,352,885'Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same'2002 6,346,463'Method for forming a semiconductor device with a tailored well profile'2002 6,337,217'Method and apparatus for improved focus in optical processing'2002 6,274,894'Low-bandgap source and drain formation for short-channel MOS transistors'2001 6,268,637'Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication'2001 6,261,908'Buried local interconnect'2001 6,259,142'Multiple split gate semiconductor device and fabrication method'2001 6,255,182'Method of forming a gate structure of a transistor by means of scalable spacer technology'2001 6,255,703'Device with lower LDD resistance'2001 6,252,283'CMOS transistor design for shared N+/P+ electrode with enhanced device performance'2001 6,242,776'Device improvement by lowering LDD resistance with new silicide process'2001 6,226,781'Modifying a design layer of an integrated circuit using overlying and underlying design layers'2001 6,225,151'Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion'2001 6,218,250'Method and apparatus for minimizing parasitic resistance of semiconductor devices'2001 6,207,563'Low-leakage CoSi2-processing by high temperature thermal processing'2001 6,201,278'Trench transistor with insulative spacers'2001 6,200,862'Mask for asymmetrical transistor formation with paired transistors'2001 6,197,645'Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls'2001 6,194,768'High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure'2001 6,188,107'High performance transistor fabricated on a dielectric film and method of making same'2001 6,188,114'Method of forming an insulated-gate field-effect transistor with metal spacers'2001 6,166,354'System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication'2000 6,163,059'Integrated circuit including source implant self-aligned to contact via'2000 6,146,983'Method of making semiconductor device having sacrificial salicidation layer'2000 6,146,978'Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance'2000 6,140,677'Semiconductor topography for a high speed MOSFET having an ultra narrow gate'2000 6,140,674'Buried trench capacitor'2000 6,140,167'High performance MOSFET and method of forming the same using silicidation and junction implantation prior to gate formation'2000 6,133,124'Device improvement by source to drain resistance lowering through undersilicidation'2000 6,127,234'Ultra shallow extension formation using disposable spacers'2000 6,127,251'Semiconductor device with a reduced width gate dielectric and method of making same'2000 6,114,229'Polysilicon gate electrode critical dimension and drive current control in MOS transistor fabrication'2000 6,114,251'Method of fabrication for ultra thin nitride liner in silicon trench isolation'2000 6,111,260'Method and apparatus for in situ anneal during ion implant'2000 6,100,146'Method of forming trench transistor with insulative spacers'2000 6,096,639'Method of forming a local interconnect by conductive layer patterning'2000 6,087,706'Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls'2000 6,084,280'Transistor having a metal silicide self-aligned to the gate'2000 6,080,629'Ion implantation into a gate electrode layer using an implant profile displacement layer'2000 6,069,384'Integrated circuit including vertical transistors with spacer gates having selected gate widths'2000 6,069,398'Thin film resistor and fabrication method thereof'2000 6,060,345'Method of making NMOS and PMOS devices with reduced masking steps'2000 6,060,389'Semiconductor fabrication employing a conformal layer of CVD deposited TiN at the periphery of an interconnect'2000 6,051,459'Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate'2000 6,048,785'Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching'2000 6,044,203'Rapid thermal anneal system and method including improved temperature sensing and monitoring'2000 6,037,244'Method of manufacturing a semiconductor device using advanced contact formation'2000 6,037,232'Semiconductor device having elevated silicidation layer and process for fabrication thereof'2000 6,037,607'Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques'2000 6,030,752'Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device'2000 6,005,272'Trench transistor with source contact in trench'1999 5,976,938'Method of making enhancement-mode and depletion-mode IGFETs with different gate thicknesses'1999 5,976,956'Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device'1999 5,970,331'Method of making a plug transistor'1999 5,962,894'Trench transistor with metal spacers'1999 5,953,613'High performance MOSFET with a source removed from the semiconductor substrate and fabrication method thereof'1999 5,950,097'Advanced isolation scheme for deep submicron technology'1999 5,937,302'Method of forming lightly doped drain region and heavily doping a gate using a single implant step'1999 5,937,299'Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls'1999 5,933,721'Method for fabricating differential threshold voltage transistor pair'1999 5,933,717'Vertical transistor interconnect structure and fabrication method thereof'1999 5,930,634'Method of making an IGFET with a multilevel gate'1999 5,930,642'Transistor with buried insulative layer beneath the channel region'1999 5,923,984'Method of making enhancement-mode and depletion-mode IGFETS with different gate materials'1999 5,923,980'Trench transistor with localized source/drain regions implanted through voids in trench'1999 5,918,129'Method of channel doping using diffusion from implanted polysilicon'1999 5,918,126'Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size'1999 5,913,106'Method for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques'1999 5,912,188'Method of forming a contact hole in an interlevel dielectric layer using dual etch stops'1999 5,899,732'Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device'1999 5,888,880'Trench transistor with localized source/drain regions implanted through selectively grown oxide layer'1999 5,888,675'Reticle that compensates for radiation-induced lens error in a photolithographic system'1999 5,885,877'Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric'1999 5,885,887'Method of making an igfet with selectively doped multilevel polysilicon gate'1999 5,877,058'Method of forming an insulated-gate field-effect transistor with metal spacers'1999 5,874,341'Method of forming trench transistor with source contact in trench'1999 5,851,891'IGFET method of forming with silicide contact on ultra-thin gate'1998 5,849,622'Method of forming a source implant at a contact masking step of a process flow'1998 5,840,451'Individually controllable radiation sources for providing an image pattern in a photolithographic system'1998 5,837,557'Semiconductor fabrication method of forming a master layer to combine individually printed blocks of a circuit pattern'1998 5,827,761'Method of making NMOS and devices with sequentially formed gates having different gate lengths'1998 5,801,075'Method of forming trench transistor with metal spacers'1998 5,759,871'Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques'1998 5,723,238'Inspection of lens error associated with lens heating in a photolithographic system'1998 5,714,392'Rapid thermal anneal system and method including improved temperature sensing and monitoring'1998 5,710,054'Method of forming a shallow junction by diffusion from a silicon-based spacer'1998 5,554,562'Advanced isolation scheme for deep submicron technology'1996 5,512,506'Lightly doped drain profile optimization with high energy implants'1996 4,705,596'Simultaneous plasma sculpturing and dual tapered aperture etch'1987 4,578,859'Implant mask reversal process'1986

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1986–1987Patents assigned to HARRIS CORP (2)· patent assignee history

1986–1987Based in Palm Bay, FL, US· patent location history

1996–2007Patents assigned to ADVANCED MICRO DEVICES INC (107)· patent assignee history

1996–2007Based in Austin, TX, US· patent location history

2000Patents assigned to ADVANCED MICRODEVICES INC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	107	1996–2007
HARRIS CORP	2	1986–1987
ADVANCED MICRODEVICES INC	1	2000

Locations

Location	Patents	Span
Austin, Texas, US	108	1996–2007
Palm Bay, Florida, US	2	1986–1987