Inventor
Jeffrey H. Oppold
Inventor
Richmond, VT, US
Overview
Patents· 8 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing30%
G11CStatic stores20%
H03KPulse technique10%
H10BElectronic memory devices10%
H10DInorganic electric semiconductor devices10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
PatentTitleYear
8,196,088'Method and structure for screening NFET-to-PFET device performance offsets within a CMOS process'20127,870,525'Slack sensitivity to parameter variation based timing analysis'20117,716,616'Slack sensitivity to parameter variation based timing analysis'20107,401,307'Slack sensitivity to parameter variation based timing analysis'20087,117,428'Redundancy register architecture for soft-error tolerance and methods of making the same'20066,917,221'Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits'20056,778,449'Method and design for measuring SRAM array leakage macro (ALM)'20046,420,746'Three device DRAM cell with integrated capacitor and local interconnect'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2012Patents assigned to IBM (8)· patent assignee history
2002–2012Based in Richmond, VT, US· patent location history
2012Patents assigned to OPPOLD JEFFREY H (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 8 | 2002–2012 |
| OPPOLD JEFFREY Hself | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Richmond, VT, US | 8 | 2002–2012 |