Inventor

JHON JHY LIAW

Inventor

TW

Overview

2021–2026

Patent span

Electricity

Primary field (CPC H)

Patents· 276 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices27%

H01LSemiconductor devices23%

H10BElectronic memory devices13%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%

B82YSpecific uses or applications of nanostructures8%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%

G11CStatic stores7%

G06FElectric digital data processing1%

H03KPulse technique1%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests0%

PatentTitleYear

12,598,785Semiconductor devices and methods of manufacturing2026 12,593,489Semiconductor structure including gate spacer layer and dielectric layer having portion lower than top surface of gate spacer layer2026 12,588,246Semiconductor structure including gate stack surrounding or wrapping around plurality of semiconductor layers or nanostructures and method for forming the same2026 12,588,245Method for manufacturing for forming source/drain contact features and devices manufactured thereof2026 12,581,705Semiconductor device including multiple stacks of semiconductor nanosheets, multiple strained layers, and dielectric wall located strained layers and method of forming the same2026 12,575,138Structure and method for FinFET device with asymmetric contact2026 12,563,829Device having a diffusion break structure extending within a fin and interfacing with a source/drain2026 12,564,037Semiconductor device with source/drain via2026 12,557,375Semiconductor devices and methods of manufacturing the same2026 12,550,425Multi-gate device structure2026 12,538,534Semiconductor structure2026 12,532,445Manufacturing method of semiconductor structure including static random access memory cell2026 12,532,504Device structure with reduced leakage current2026 12,520,520Isolation structure for isolating source/drain region structure from adjacent source/drain structure2026 12,520,574Semiconductor device structure including forksheet transistors and methods of forming the same2026 12,520,471Memory device2026 12,520,469Integrated circuits with contacting gate structures2026 12,512,148Gate-all-around memory devices2025 12,501,696FinFET devices with dummy fins having multiple dielectric layers2025 12,493,733Interconnect structure design2025 12,490,509Method of manufacturing semiconductor devices and a semiconductor device2025 12,484,301Semiconductor structure with backside power mesh and method of forming the same2025 12,476,187Method and structure for metal tracks in semiconductor devices2025 12,469,548Semiconductor device2025 12,464,816Semiconductor device and method for forming the same2025 12,464,763Hybrid nanostructure and fin structure device2025 12,464,804Semiconductor structure and method for forming the same2025 12,457,796Manufacturing method of semiconductor device having frontside and backside contacts2025 12,453,164Dielectric fins with different dielectric constants and sizes in different regions of a semiconductor device2025 12,451,427Fuse cell structure2025 12,453,155Stacked gate spacers2025 12,453,070FinFET SRAM cells with dielectric fins2025 12,432,896Nanostructure field-effect transistors including source/drain features with asymmetrical depth2025 12,432,962FinFET device with source/drain contact extending over dielectric gate2025 12,424,274Memory device and manufacturing thereof2025 12,426,310Gate-all-around devices with optimized gate spacers and gate end dielectric2025 12,424,520Semiconductor device with back-side via structure2025 12,419,025Integrated circuit structure2025 12,419,026Memory structure2025 12,414,281Implantations for forming source/drain regions of different transistors2025 12,412,777Reducing parasitic capacitance in field-effect transistors2025 12,414,282Semiconductor device2025 12,414,354Semiconductor strutures with dielectric fins2025 12,414,332Structure and method for semiconductor devices2025 12,414,365Metal gate stacks and methods of fabricating the same in multi-gate field-effect transistors2025 12,414,355Semiconductor device and manufacturing method thereof2025 12,408,425Semiconductor structure with high integration density and method for manufacturing the same2025 12,408,415Semiconductor device and manufacturing method thereof2025 12,408,442Semiconductor device layout2025 12,400,713Memory cell2025 12,394,663Isolation with multi-step structure2025 12,396,210Semiconductor devices and methods for fabrication thereof2025 12,389,645Semiconductor structure with extended contact structure2025 12,382,676Semiconductor device structure and methods of forming the same2025 12,382,622Memory structure2025 12,374,390SRAM cells with vertical gate-all-round MOSFETs2025 12,368,060Semiconductor devices and methods of manufacturing2025 12,361,985Memory device2025 12,362,009SRAM performance optimization via transistor width and threshold voltage tuning2025 12,363,949Gate-all-around devices with optimized gate spacers and gate end dielectric2025 12,356,601Memory cell design2025 12,356,708Dimension variations in semiconductor devices and method for manufacturing same2025 12,354,953Via structures2025 12,347,489Content addressable memory array device structure2025 12,334,439Interconnect structure in semiconductor devices2025 12,336,282Semiconductor device having different source/drain junction depths and fabrication method thereof2025 12,324,247Integrated standard cell structure2025 12,324,235Semiconductor device and method of forming the same2025 12,324,222Semiconductor device with contracted isolation feature2025 12,324,224Method of fabricating Fin-type field-effect transistor device having substrate with heavy doped and light doped regions2025 12,317,601Dual-port SRAM structure2025 12,317,549Dielectric fin structures with varying height2025 12,317,468Memory device and manufacturing thereof2025 12,317,567Semiconductor device structure and method for forming the same2025 12,300,690Static random access memory device2025 12,294,017Semiconductor gate-all-around structure having carbon-doped anti-punch-through (APT) layers over wells2025 12,283,311Memory device and method for forming the same2025 12,283,587Integrated circuit and method of forming the same2025 12,284,797Memory device and manufacturing thereof2025 12,267,991Multi-gate field-effect transistors in integrated circuits2025 12,266,686Leakage reduction in gate-all-around devices2025 12,266,653Semiconductor structure and methods of forming the same2025 12,261,214Multi-gate transistor structure2025 12,230,633Integrated circuit structure including multi-width semiconductor fins2025 12,219,746Semiconductor structure and method for forming the same2025 12,218,137Structure and method for gate-all-around metal-oxide-semiconductor devices with improved channel configurations2025 12,218,139Semiconductor device with metal structure2025 12,213,296IC including standard cells and SRAM cells2025 12,205,849Semiconductor device structure with source/drain structure and method for forming the same2025 12,199,100Multi-gate device integration with separated fin-like field effect transistor cells and gate-all-around transistor cells2025 12,184,283Semiconductor device for logic and memory co-optimization2024 12,183,791Integrated circuit structure2024 12,183,735Semiconductor devices and methods of manufacture2024 12,183,652Integrated circuit structure2024 12,176,411Semiconductor device with isolation transistors and back side voltage metal lines2024 12,159,913Contact structures for gate-all-around devices and methods of forming the same2024 12,159,872IC including standard cells and SRAM cells2024 12,154,959Gate-all-around structures and manufacturing method thereof2024 12,148,463Dual port memory cell with multiple metal layers2024 12,136,571Methods for fabricating FinFETs having different fin numbers and corresponding FinFETs thereof2024 12,127,387Gate-all-around high-density and high-speed SRAM cells2024 12,119,379Gate all around transistors with different threshold voltages2024 12,114,473Three-port SRAM cell and layout method2024 12,106,801Circuit for reducing voltage degradation caused by parasitic resistance in a memory device2024 12,108,586Two-port SRAM structure2024 12,100,628Interconnect structure for fin-like field effect transistor2024 12,094,953Semiconductor manufacturing2024 12,089,389Conductive layers with different thicknesses2024 12,089,390Cell manufacturing2024 12,089,391Semiconductor device2024 12,080,607Structure and method for FinFET device with source/drain modulation2024 12,082,389Integrated circuit with embedded high-density and high-current SRAM macros2024 12,074,057Isolation structures2024 12,057,487Memory chip structure having GAA transistors with different threshold voltages and work functions for improving performances in multiple applications2024 12,051,695Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same2024 12,046,684Semiconductor structure having both gate-all-around devices and planar devices2024 12,048,136Semiconductor structure with dielectric fin in memory cell and method for forming the same2024 12,041,767Fuse cell structure2024 12,041,761SRAM circuits with aligned gate electrodes2024 12,033,940Semiconductor device and method2024 12,034,007Fin-based device having an isolation gate interfacing with a source/drain2024 12,021,023Semiconductor device with source/drain via2024 12,022,644Semiconductor structure with a bit line in a different configuration than a local interconnect line2024 12,009,426Structure and method for FinFET device with asymmetric contact2024 11,996,320Reducing parasitic capacitance in field-effect transistors2024 11,996,360Semiconductor device and manufacturing method thereof2024 11,997,844SRAM structures with improved write word line placement2024 11,991,872Semiconductor device with gate recess and methods of forming the same2024 11,990,525Isolation structure for isolating epitaxially grown source/drain regions and method of fabrication thereof2024 11,980,014Memory devices with gate all around transistors2024 11,980,015SRAM cell and logic cell design2024 11,978,732Methods of manufacturing semiconductor devices2024 11,968,819Gate-all-around field-effect transistors in integrated circuits2024 11,967,532Gate spacers and methods of forming the same in semiconductor devices2024 11,955,486Integrated circuit device and method of forming the same2024 11,955,425Interconnect structure for logic circuit2024 11,950,401Two-port SRAM cells with asymmetric M1 metalization2024 11,948,940Multi-gate device structure2024 11,935,882Static random access memory device2024 11,925,011Fin-based strap cell structure for improving memory performance2024 11,923,413Semiconductor structure with extended contact structure2024 11,915,946Semiconductor devices and methods of manufacturing2024 11,916,055Semiconductor structure having logic cells with multiple cell heights2024 11,908,864Method of manufacturing semiconductor devices and a semiconductor device2024 11,910,586Integrated circuit and static random access memory thereof2024 11,901,352Dual-port SRAM structure2024 11,895,819Implantations for forming source/drain regions of different transistors2024 11,871,552Memory cell structure2024 11,869,892Semiconductor device structure and methods of forming the same2024 11,856,746Well strap structures and methods of forming the same2023 11,855,094FinFET devices with dummy fins having multiple dielectric layers2023 11,855,072Integrated standard cell structure2023 11,830,878Structure and method for gate-all-around metal-oxide-semiconductor devices with improved channel configurations2023 11,832,431Method for manufacturing static random access memory device2023 11,810,981Semiconductor structure having both gate-all-around devices and planar devices2023 11,804,485Semiconductor devices and methods of manufacture2023 11,791,217Gate structure and method with dielectric gates and gate-cut features2023 11,791,337Integrated circuit structure including multi-length source/drain contacts2023 11,792,970IC including standard cells and SRAM cells2023 11,791,339Multi-gate device integration with separated fin-like field effect transistor cells and gate-all-around transistor cells2023 11,792,971FinFET SRAM cells with dielectric fins2023 11,784,180Semiconductor device layout2023 11,784,226Semiconductor gate-all-around device having an anti-punch-through (APT) layer including carbon2023 11,764,112Methods for fabricating FinFETs having different fin numbers and corresponding FinFETs thereof2023 11,764,287Multi-gate transistor structure2023 11,758,714Fuse cell structure2023 11,757,014Memory chip structure having GAA transistors with different threshold voltages and work functions for improving performances in multiple applications2023 11,756,962Semiconductor device2023 11,749,677Semiconductor structure and methods of forming the same2023 11,742,349Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same2023 11,742,347Fin end isolation structure for semiconductor devices2023 11,728,206Isolation with multi-step structure2023 11,728,431Inner spacers for gate-all-around semiconductor devices2023 11,728,382Gate all around transistors with different threshold voltages2023 11,728,402Structure and method for semiconductor devices2023 11,728,411Stacked gate spacers2023 11,721,695Metal gate stacks and methods of fabricating the same in multi-gate field-effect transistors2023 11,721,701Semiconductor circuit with metal structure and manufacturing method2023 11,721,589Fin-type field-effect transistor device having substrate with heavy doped and light doped regions, and method of fabricating the same2023 11,723,193Memory devices and methods of manufacturing thereof2023 11,710,522SRAM array2023 11,696,430Two-port SRAM structure2023 11,688,456Gate-all-around memory devices2023 11,688,791Gate structure and method2023 11,682,450SRAM performance optimization via transistor width and threshold voltage tuning2023 11,682,672Semiconductor device and method for forming the same2023 11,676,869Semiconductor device and manufacturing method thereof2023 11,676,654SRAM structure with reduced capacitance and resistance2023 11,670,678Integrated circuit structure2023 11,670,703Fin and gate dimensions for optimizing gate formation2023 11,659,703Integrated circuit with embedded high-density and high-current SRAM macros2023 11,658,074Structure and method for FinFET device with source/drain modulation2023 11,651,804Memory macro and method of operating the same2023 11,640,962Semiconductor structure2023 11,616,125Integrated circuit device and manufacturing method thereof2023 11,605,637SRAM circuits with aligned gate electrodes2023 11,600,624Semiconductor structure with dielectric fin in memory cell and method for forming the same2023 11,587,872Interconnect structure for improving memory performance and/or logic performance2023 11,587,926Semiconductor structure2023 11,581,414Gate-all-around devices with optimized gate spacers and gate end dielectric2023 11,581,321SRAM structures with improved write word line placement2023 11,581,256Interconnect structure for logic circuit2023 11,575,050Semiconductor structure having both gate-all-around devices and planar devices2023 11,569,247Semiconductor structure2023 11,563,087Fin-based strap cell structure2023 11,552,083Integrated circuits with contacting gate structures2023 11,545,212Dual port SRAM cell with dummy transistors2023 11,545,573Hybrid nanostructure and fin structure device2023 11,532,623Semiconductor structure having gate-all-around devices2022 11,532,502Reducing parasitic capacitance in field-effect transistors2022 11,532,554Interconnect device and method2022 11,527,540Implantations for forming source/drain regions of different transistors2022 11,527,651FinFET device with contact over dielectric gate2022 11,514,952Memory device with strap cells2022 11,515,199Semiconductor structures including standard cells and tap cells2022 11,508,735Cell manufacturing2022 11,508,737SRAM cell and logic cell design2022 11,502,004Configuring different via sizes for bridging risk reduction and performance improvement2022 11,495,662Gate all around transistors with different threshold voltages2022 11,495,537Interconnect structure in semiconductor devices2022 11,488,969Two-port SRAM cells with asymmetric M1 metalization2022 11,488,966FinFET SRAM having discontinuous PMOS fin lines2022 11,488,968Integrated circuit and static random access memory thereof2022 11,476,278IC including standard cells and SRAM cells2022 11,462,614Semiconductor devices and methods of manufacturing2022 11,456,228Integrated circuit structure2022 11,444,072Dual-port SRAM structure2022 11,444,089Gate-all-around field effect transistors in integrated circuits2022 11,437,373Multi-gate device structure2022 RE049203Layout for multiple-fin SRAM cell2022 11,430,508Circuit for reducing voltage degradation caused by parasitic resistance in a memory device2022 11,410,719SRAM array2022 11,411,090Contact structures for gate-all-around devices and methods of forming the same2022 11,404,423Fin-based strap cell structure for improving memory performance2022 11,393,750Semiconductor device and manufacturing method thereof2022 11,393,817Structure and method for gate-all-around metal-oxide-semiconductor devices with improved channel configurations2022 11,373,993Integrated standard cell structure2022 11,374,088Leakage reduction in gate-all-around devices2022 11,374,006Semiconductor device and method of forming the same2022 11,367,663Interconnect structure for fin-like field effect transistor2022 11,367,782Semiconductor manufacturing2022 11,355,363Semiconductor devices and methods of manufacturing2022 11,355,502Semiconductor device with gate recess and methods of forming the same2022 11,355,501Method for manufacturing static random access memory device2022 11,349,027Structure and method for FinFET device with asymmetric contact2022 11,348,926Conductive layers with different thicknesses2022 11,349,002Isolation structure for for isolating epitaxially grown source/drain regions and method of fabrication thereof2022 11,342,337Structure and method for FinFET SRAM2022 11,302,692Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same2022 11,296,202Memory chip structure having GAA transistors with different threshold voltages and work functions for improving performances in multiple applications2022 11,282,751Dielectric fins with different dielectric constants and sizes in different regions of a semiconductor device2022 11,282,859Semiconductor circuit with metal structure and manufacturing method2022 11,276,696SRAM structure and method for manufacturing SRAM structure2022 11,277,136Semiconductor device for logic and memory co-optimization2022 11,270,996FinFET devices with dummy fins having multiple dielectric layers2022 11,264,385Fin-based device having an isolation gate in physical contact with a source/drain2022 11,257,761Logic cell structure and method2022 11,257,930Method of forming fin field effect transistor2022 11,251,091Semiconductor device with contracted isolation feature2022 11,251,069Method for forming isolation with multi-step structure2022 11,245,005Method for manufacturing semiconductor structure with extended contact structure2022 11,239,339Gate structure and method2022 11,239,335Structure and method for semiconductor devices2022 11,222,898Two-port SRAM structure2022 11,210,447Reconfiguring layout and sizing for transistor components to simultaneously optimize logic devices and non-logic devices2021 11,211,387Fin-based strap cell structure for improving memory performance2021 11,201,159SRAM structure and connection2021 11,195,937Multi-gate transistor structure2021 11,195,760Fin-type field-effect transistor device having substrate with heavy doped and light doped regions, and method of fabricating the same2021 11,189,340Circuit in memory device for parasitic resistance reduction2021 11,164,746Method of manufacturing semiconductor devices and a semiconductor device2021 11,158,632Fin-based strap cell structure for improving memory performance2021 11,158,741Nanostructure device and method2021 11,152,488Gate-all-around structure with dummy pattern top in channel region and methods of forming the same2021 11,145,660Dual-port SRAM cell structure2021 11,145,599Method of fabricating a memory device having multiple metal interconnect lines2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (273)· patent assignee history

2021–2026Based in TW· patent location history

2022Patents assigned to TAIWAN SEMICONDUCTOR MANUFACIURING COMPANY LTD (1)· patent assignee history

2024Patents assigned to TAIWAN SEMICONDUCOTR MFG CO LTD (1)· patent assignee history

2025–2026Patents assigned to PARABELLUM STRATEGIC OPPORTUNITIES FUND LLC (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	273	2021–2026
PARABELLUM STRATEGIC OPPORTUNITIES FUND LLC	3	2025–2026
TAIWAN SEMICONDUCOTR MFG CO LTD	1	2024
TAIWAN SEMICONDUCTOR MANUFACIURING COMPANY LTD	1	2022

Locations

Location	Patents	Span
TW	276	2021–2026