Inventor
Yong-Gill Lee
Inventor
Kaohsiung, TW
Overview
Patents· 4 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1080%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
PatentTitleYear
7,211,467'Method for fabricating leadless packages with mold locking characteristics'20077,125,747'Process for manufacturing leadless semiconductor packages including an electrical test in a matrix of a leadless leadframe'20067,087,462'Method for forming leadless semiconductor packages'20066,984,878'Leadless leadframe with an improved die pad for mold locking'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2007Patents assigned to ADVANCED SEMICONDUCTOR ENG (4)· patent assignee history
2006–2007Based in Kaohsiung, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED SEMICONDUCTOR ENG | 4 | 2006–2007 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kaohsiung, TW | 4 | 2006–2007 |