Inventor
Krishnendu Mondal
Inventor
Bangalore, IN
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores72%
G01RMeasuring electric variables10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
G06FElectric digital data processing3%
H01LSemiconductor devices3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
PatentTitleYear
10,971,243Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register202110,692,584Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register202010,658,062Simultaneous scan chain initialization with disparate latches202010,586,606Simultaneous scan chain initialization with disparate latches202010,553,302Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register202010,199,121Simultaneous scan chain initialization with disparate latches201910,096,377Simultaneous scan chain initialization with disparate latches201810,026,498Simultaneous scan chain initialization with disparate latches201810,014,074Failure analysis and repair register sharing for memory BIST20189,881,694'Built-in-self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register'20189,859,019'Programmable counter to control memory built in self-test'20189,773,570'Built-in-self-test (BIST) test time reduction'20179,761,329'Built-in self-test (BIST) circuit and associated BIST method for embedded memories'20179,715,942'Built-in self-test (BIST) circuit and associated BIST method for embedded memories'20178,918,690'Decreasing power supply demand during BIST initializations'20148,914,688'System and method of reducing test time via address aware BIST circuitry'20148,872,322'Stacked chip module with integrated circuit chips having integratable built-in self-maintenance blocks'20148,853,847'Stacked chip module with integrated circuit chips having integratable and reconfigurable built-in self-maintenance blocks'20146,928,377'Self-test architecture to implement data column redundancy in a RAM'20056,922,649'Multiple on-chip test runs and repairs for memories'20056,768,694'Method of electrically blowing fuses under control of an on-chip tester interface apparatus'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2021Patents assigned to IBM (19)· patent assignee history
2004–2005Based in Burlington, VT, US· patent location history
2014Patents assigned to INTERNAT BUSINESSS MACHINES CORP (1)· patent assignee history
2014–2021Based in Bangalore, IN· patent location history
2017–2018Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 19 | 2004–2021 |
| GLOBALFOUNDRIES INC | 2 | 2017–2018 |
| INTERNAT BUSINESSS MACHINES CORP | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bangalore, IN | 18 | 2014–2021 |
| Burlington, VT, US | 3 | 2004–2005 |