Inventor
Robert J. Devins
Inventor
Essex Junction, VT, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing73%
G01RMeasuring electric variables17%
G06TImage data processing or generation, in general10%
PatentTitleYear
9,367,493'Method and system of communicating between peer processors in SoC environment'20168,234,624'System and method for developing embedded software in-situ'20128,140,314'Optimal bus operation performance in a logic simulation environment'20127,917,348'Method of switching external models in an automated system-on-chip integrated circuit design verification system'20117,849,362'Method and system of coherent design verification of inter-cluster interactions'20107,729,877'Method and system for logic verification using mirror interface'20107,711,534'Method and system of design verification'20107,451,070'Optimal bus operation performance in a logic simulation environment'20087,353,131'Method and system for logic verification using mirror interface'20087,353,156'Method of switching external models in an automated system-on-chip integrated circuit design verification system'20087,176,927'Method and system for graphics rendering using hardware-event-triggered execution of captured graphics hardware instructions'20076,952,215'Method and system for graphics rendering using captured graphics hardware instructions'20056,868,545'Method for re-using system-on-chip verification software in an operating system'20056,865,502'Method and system for logic verification using mirror interface'20056,762,761'Method and system for graphics rendering using hardware-event-triggered execution of captured graphics hardware instructions'20046,658,633'Automated system-on-chip integrated circuit design verification system'20036,615,167'Processor-independent system-on-chip verification for embedded processor systems'20036,571,373'Simulator-independent system-on-chip verification methodology'20036,539,522'Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs'20036,525,738'Display list processor for decoupling graphics subsystem operations from a host processor'20036,487,699'Method of controlling external models in system-on-chip verification'20026,427,224'Method for efficient verification of system-on-chip integrated circuit designs including an embedded processor'20025,784,595'DMA emulation for non-DMA capable interface cards'19985,768,631'Audio adapter card and method for trapping audio command and producing sound corresponding to the trapped command'19985,668,957'Method and apparatus for providing virtual DMA capability on an adapter connected to a computer system bus with no DMA support'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2012Patents assigned to IBM (24)· patent assignee history
1997–2016Based in Essex Junction, VT, US· patent location history
2012–2016Patents assigned to DEVINS ROBERT J (3)· patent assignee history
2012–2016Patents assigned to MILTON DAVID W (2)· patent assignee history
2012Patents assigned to DHANWADA NAGASHYAMALA R (1)· patent assignee history
2016Patents assigned to GLOBALFOUNDRIES INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 24 | 1997–2012 |
| DEVINS ROBERT Jself | 3 | 2012–2016 |
| MILTON DAVID W | 2 | 2012–2016 |
| DHANWADA NAGASHYAMALA R | 1 | 2012 |
| GLOBALFOUNDRIES INC | 1 | 2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 25 | 1997–2016 |